Apparatus and method for error correction and error detection

ABSTRACT

A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No.13/975,621, filed on Aug. 26, 2013, which is a continuation of U.S.application Ser. No. 12/943,520, filed on Nov. 10, 2010.

FIELD

Embodiments according to the invention relate to error correction anderror detection of digital signals and particularly to an apparatus anda method for correcting at least one bit error within a coded bitsequence.

BACKGROUND

Due to the high integration density of electronic circuits and storages,the frequency of errors increases.

Apart from 1-Bit-errors, increasingly also 2-Bit-errors and generalmulti-bit errors are to be considered, i.e. to be corrected and to bedetected. In particular, in error correction it is important to correctthe occurred errors quickly, if possible within the current clock cyclein order to prevent a delayed processing of the corrected data ascompared to the uncorrected data.

Frequently, data are written into a storage under an address and readout after some time. Here it is possible that the data when read out ofthe storage are faulty or corrupt and have to be corrected after readingit out.

Here, both one bit errors, two bit errors and generally multi-bit errorsoccur, which are caused randomly with decreasing probability, and alsoerrors occur in which all memory cells take on the value 0 erroneously,which is to be referred to as “All-0”, and also errors where all memorycells take on the value 1, to be referred to here as “All-1”.

It is also of special interest to detect possible address errors with ahigh probability, as a faulty address for example when reading out of astorage, may lead to completely different data. It is possible tocorrect one bit errors by Hamming code or Hsia-codes and 2-Bit-errorsrelatively fast by BCH-Codes implemented in parallel.

Disadvantageous with prior solutions for 1-bit and 2-bit errorcorrection is, for example, that the errors “All-0” and “All-1” are notpart of error detection. Generally, it is of high interest to improvethe reliability of error correction and error detection concepts.

SUMMARY

A syndrome generator for forming an error syndrome of a linear code C oflength n with an H-matrix H=(h₁, . . . , h_(n)) of n columns h₁, . . . ,h_(n) of m components each such that the H-matrix is an (m, n)-matrix,wherein a codeword v=v₁, . . . , v_(n) of the code C comprises a firstsubword x₁, . . . , x_(k+m) of length k+m and a second subword a₁, . . ., a_(l) of length l, wherein n=k+l+m. The code C is configured forcorrecting 1, . . . , t-bit errors in bits of the first subword and todetect 1, . . . , l bit errors in bits of the second subword so that thecolumns of the H-matrix H corresponding to the bits of the first subwordare forming a first (m, k+m)-sub-matrix H^(x)=(h₁ ^(x), . . . , h_(k+m)^(x)) and so that the columns of the H-matrix H corresponding to thebits of the second subword are forming a second sub-matrix H^(a)=(h₁^(a), . . . , h_(l) ^(a)). All linear combinations of up to t columns ofthe first submatrix H^(x), which do not result in the zero vector, arepairwise different. Moreover, all linear combinations of the columns ofthe second submatrix H^(a) are different from all linear combinations ofup to t columns of the first sub-matrix H^(x), which do not result inthe zero vector, wherein t≧1, k>0, k+m≧4, and l>t+1.

Moreover, a syndrome generator for forming an error syndrome of a linearcode C of length n having m check bits and an H-matrix H is provided,wherein a codeword v=v₁, . . . , v_(n) of the code C comprises a firstsubword u₁, . . . , u_(k), c₁, . . . , c_(m) of length k+m and a secondsubword a₁, . . . , a_(l) of length l with n=k+m+l. The code C isconfigured for correcting 1-bit, . . . , t-bit errors in bits of thefirst subword u₁, . . . , u_(k), c₁, . . . , c_(m) and to detect errorsin bits of the second subword a₁, . . . , a_(l). The H-matrix H=(H^(u),H^(a), H^(c)) of the code C is determined so that it consists of a first(m, k+m)-sub-matrix H^(x)=(H^(u), H^(c))=(h₁ ^(x), . . . , h_(k+m) ^(x))having k+m columns with m components and a second (m, l)-sub-matrixH^(y)=H^(a)=(h₁ ^(y), . . . , h_(l) ^(y)) having l columns with mcomponents, so that an error syndrome is associated to each 1-bit, . . ., t-bit error in the bits u₁, . . . , u_(k), c₁, . . . , c_(m), so thatpairwise different error syndromes unequal 0 are associated to differenterrors of said errors, respectively, and so that to each 1-bit error, .. . n-bit error in the bits a₁, . . . , a_(l), an error syndrome isassociated that differs from each error syndrome of a 1-bit error, . . ., t-bit error in the bits u₁, . . . , u_(k), . . . , c_(m). The firstsub-matrix H^(x) is an H-matrix of a linear t-bit error correcting codeof the length k+m, and wherein an arbitrary linear combination of thecolumns h₁ ^(y), . . . , h_(l) ^(y) of the second sub-matrix H^(y) isunequal to an arbitrary linear combination of t columns of the firstsub-matrix H^(x), wherein t≧1, k+m≧4, and l>t+1.

Moreover, a circuitry comprising a syndrome generator configured togenerate a syndrome based on a parity check matrix and a binary wordcomprising a first set of bits and a second set of bits is provided. Forthe first set of bits an error correction of one or more correctable biterrors within the first set is provided by the parity check matrix andfor the second set of bits an error detection of one or more detectablebit errors within the second set is provided by the parity check matrix.The parity check matrix comprises a first subset of columns that areassociated with the first set of bits within the binary word, and asecond subset of columns that are associated with the second set of bitswithin the binary word. Syndromes generated by the first subset ofcolumns in case one of the one or more correctable errors occurs withinthe first set of bits are all pairwise different for the one or morecorrectable errors and are also different from all syndromes generatedby the second subset of columns in case an arbitrary error occurs withinthe second set of bits.

An embodiment of the invention provides an apparatus for correcting atleast one bit errors within a coded bit sequence. The apparatuscomprises an error syndrome generator and a bit error corrector. Theerror syndrome generator is configured to determine an error syndrome ofa coded bit sequence derived by a multiplication of a check matrix withthe coded bit sequence. The check matrix comprises a first sub-matrix, asecond sub-matrix and a third sub-matrix. Each sub-matrix comprises aplurality of lines, wherein each line comprises a plurality of binarycomponents. Further, at least a first predefined component or a secondpredefined component of each line of the first sub-matrix comprises afirst bit value. The second sub-matrix comprises lines being linearlyindependent from each other and the first predefined component and thesecond predefined component of each line of the second sub-matrixcomprises a same second bit value. The third sub-matrix comprises linesbeing linearly independent from each other and the first predefinedcomponent or the second predefined component of each line of the thirdsub-matrix comprises the first bit value. Further, an XOR-sum of thefirst predefined components of all lines of the first sub-matrix and thethird sub-matrix is equal to the second bit value and an XOR-sum of thesecond predefined components of all lines of the first sub-matrix andthe third sub-matrix is equal to 0. Additionally, a result of amultiplication of the check matrix and a test vector is equal to aresult of a multiplication of the second sub-matrix and a resultingvector, wherein at least one component of the resulting vector comprisesthe second bit value. Further, the bit error corrector is configured tocorrect a bit error within the coded bit sequence based on thedetermined error syndrome of the coded bit sequence.

By using an error syndrome determined according to a check matrix withproperties described above, the error correction and error detectionabilities of the proposed concept may be significantly better than withknown concepts. For example, the proposed concept enables one todifferentiate every 1-bit error from All-1-errors or All-0-errors. Thus,it may not be the case that a word, which is read out of a storage, incase of a correctable 1-bit error is mixed up with an All-0-error or anAll-1-error.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments according to the invention will be detailed subsequentlyreferring to the appended drawings, in which:

FIG. 1 is a block diagram of an apparatus for correcting at least onebit error within a coded bit sequence;

FIG. 2 is a schematic illustration of a coding under consideration ofaddress bits;

FIG. 3 is a schematic illustration of a coding for a separated H-matrixunder consideration of address bits;

FIG. 4 is a schematic illustration of an integration of a syndromegenerator;

FIG. 5 is a schematic illustration of an integration of a syndromegenerator including an all 0 and all 1 detection;

FIG. 6 is a schematic illustration of a derivation of a correctionvector for data bits;

FIG. 7 is a schematic illustration of a derivation of a correctionvector for data and check bits;

FIG. 8 is a schematic illustration of a derivation of a correctionvector for data, check and address bits;

FIG. 9 is a schematic illustration of a generation of an address errorsignal;

FIGS. 10, 11, 12, and 13 are schematic illustrations of a derivation ofa correction signal;

FIGS. 14 a-14 i are schematic illustrations of a determination ofcorrection values; and

FIG. 15 is a block diagram of a decoder for decoding a faulty, coded bitsequence;

FIG. 16 is a flowchart of a method for correcting at least one bit errorwithin a coded bit sequence;

FIG. 17 schematically illustrates a Venn Diagram of a Galois fieldGF(2^(M)) and some of its subsets, the elements of which may be used ascolumns in sub-matrices of the parity check matrix;

FIG. 18 schematically shows a circuitry with an addressable memory and aconnected syndrome generator arrangement,

FIG. 19 schematically shows a syndrome generator arrangement with asyndrome generator and a combinational circuit for compacting a readaddress,

FIG. 20 schematically shows a circuitry using a first combinationalcircuit compacting the write address and a second combinational circuitfor compacting the read address,

FIG. 21 schematically shows a special implementation example of theinvention, wherein various sub circuits are used commonly for both whenwriting and reading data,

FIG. 22 schematically shows the sub circuits of FIG. 4, that are activeduring reading,

FIG. 23 schematically shows the sub circuits of FIG. 4, that are activeduring writing,

FIG. 24 schematically shows a syndrome generator arrangement and anerror detection circuit downstream thereof,

FIG. 25 schematically shows an illustration of a special implementationexample of an error detection circuit comprising two sub circuits,

FIG. 26 schematically shows a circuitry for compacting of address bits,

FIG. 27 schematically shows a circuitry for modifying of, for example,linearly compacted address bits in non-linearly compacted address bits.

FIG. 28 shows a syndrome generator of an embodiment having an n-bit wideinput for inputting an n-bit wide binary word and having an m-bit wideoutput connected to an m-bit wide input of a subcircuit,

FIG. 29 shows the subcircuit Cor/Det 120 of FIG. 28 according to anembodiment,

FIG. 30 shows a read out of bits from an addressable memory from a readaddress according to an embodiment,

FIG. 31 shows a read out of bits from an addressable memory according toanother embodiment,

FIG. 32 shows a syndrome generator according to an embodiment,

FIG. 33 shows a read out of bits from an addressable memory according toa further embodiment,

FIG. 34 shows a syndrome generator according to another embodiment, and

FIG. 35 illustrates an embodiment, where the parity of bits to becorrected is integrated into the formation of the H matrix of the usedcode C.

DETAILED DESCRIPTION

In the following, the same reference numerals are partly used forobjects and functional units having the same or similar functionalproperties and the description thereof with regard to a figure shallapply also to other figures in order to reduce redundancy in thedescription of the embodiments.

A syndrome generator for forming an error syndrome of a linear code C oflength n with an H-matrix H=(h₁, . . . , h_(n)) of n columns h₁, . . . ,h_(n) of m components each such that the H-matrix is an (m, n)-matrix,wherein a codeword v=v₁, . . . , v_(n) of the code C comprises a firstsubword x₁, . . . , x_(k+m) of length k+m and a second subword a₁, . . ., a_(l) of length l with n=k+m+l. The code C is configured forcorrecting 1, . . . , t-bit errors in bits of the first subword and todetect 1, . . . , l bit errors in bits of the second subword so that thecolumns of the H-matrix H corresponding to the bits of the first subwordare forming a first (m, k+m)-sub-matrix H^(x)=(h₁ ^(x), . . . , h_(k+m)^(x)) and so that the columns of the H-matrix H corresponding to thebits of the second subword are forming a second sub-matrix H^(a)=(h₁^(a), . . . , h_(l) ^(a)). All linear combinations of all subsets of upto t columns of the first submatrix H^(x), which do not result in thezero vector, are pairwise different. Moreover, all linear combinationsof all subsets of the columns of the second submatrix H^(a) aredifferent from all linear combinations of all subsets of up to t columnsof the first sub-matrix H^(x), which do not result in the zero vector,wherein t≧1, k>0, k+m≧4, and l>t+1.

Before the proposed concept is described in greater detail, sometheoretical basics and basic terms on linear block codes, in particularHamming codes, Hsiao codes and BCH-codes are briefly presented. Forexample, these are also described in “Fujiwara, E., Code Design forDependable Systems, Wiley, 2006, p. 49-53, p. 98-101 and in Tzschach, H.and Haflinger, G., Codes für den störungsgesicherten Datentransfer,Oldenburg Verlag, 1993, p. 111-121”.

A Hamming code is a linear block code with a code distance 3. If m isthe number of check bits, its length is n=2^(m)−1. The number of databits is k=2^(m)−1−m. As any linear code, the Hamming code may as usualbe described by a generator matrix G, briefly G-matrix, and a checkmatrix H (also called parity-check matrix), briefly H matrix. The checkmatrix of a unshortened Hamming code is an (m,n) matrix whose columnsare any possible different 2^(m)−1 binary vectors unequal to 0. Thesecolumns are also described as m-digit binary numbers, and the followingapplies

H=(h ₁ , . . . , h ₂ _(m) ⁻¹)=(1_(bin),2_(bin), . . . ,[2^(m)−1]_(bin)),

wherein i_(bin) designates the representation of i as an m-digit binarynumber.

A Hamming code may be shortened, as any other linear block code byeliminating a certain number of columns in the check matrix of theunshortened code. Apart from that, columns may also be exchanged in thusthe check matrix may be transformed.

From the check matrix of a linear code a generator matrix may bedetermined, briefly called G matrix. The generator matrix is a (k,n)matrix. If k information bits u₁, . . . , u_(k) are present, the sameare coded by the generator matrix into a code word v

v=(v ₁ , . . . , v _(n))=u·G=(u ₁ , . . . , u _(k))·G

If a word v′=v′₁, . . . , v′_(n) is checked whether it is a code word, asyndrome S is formed, with

S=H·v′ ^(T)

with S=S₁, . . . , S_(m). If S=0, no error is detected. If S=h_(i), a1-bit error is present in the i-th bit of v′.

The error correction of the bits v′₁, . . . , v′_(n) may be done bycorrection circuits K₁, . . . , K_(n) which determine a correction valueΔv_(i) from the error syndrome S, which is XORed (linked by a logicalXOR function) with v′_(i). For i=1, . . . , n in case of a 1-bit errorthe correction circuit K, outputs a value 1, if S=h_(i). If the errorsyndrome is equal to 0, the correction circuit K_(i) outputs the value0.

A Hsiao-code is a linear code with a code distance of 4. If theHsiao-code has m check bits, its check matrix H consists of all m-digitbinary vectors comprising an odd number of ones. The length of an(unshortened) Hsiao-code with m check bits is n=2^(m−1), as there are2^(m−1) different m-digit binary vectors having an odd number of ones.By deleting columns and by reordering columns of the unshortenedHsiao-code, a check matrix of a shortened Hsiao-code is obtained.Testing a word v′=v′₁, . . . , v′_(n) is again done by checking theerror syndrome

S=H·v′ ^(T)

If S=h_(j), i.e. equal to the j-th column of the check matrix, a 1-biterror is corrected in the j-th bit, by XOR-ing (applying a logicalXOR-function) a correction value Δv_(j)=1 with v′_(j). This correctionvalue Δv_(j) may be determined from the error syndrome S by a correctioncircuit K_(j). The correction circuit K_(j) then outputs a value 1, ifS=h_(j). If S is a binary vector with an even number of ones, anincorrectable error is indicated.

As the application of the proposed concept to BCH-codes(Bose-Chaudhuri-Hocquenghem-Codes) is also of special interest, somecharacteristics of BCH-codes are to be described. For example, they arealso described in “Tzschach, H. and Haβlinger, G.: Codes für denstörungssicheren Datentransfer, Oldenburg Verlag 1993, p. 111-121” and“Lin, S., Costello, D.: Error Control Coding, Prentice Hall, 1983,chapter 6”.

A BCH-code is a special cyclic code and thus a linear code. A BCH-codemay be described as a cyclic code by a special generator polynomial G(z)and as a linear code by a generator matrix G and by a check matrix H.

In case of a 2-bit error correcting BCH-code, the generator polynomialmay in its simplest form be represented as

G(z)=m _(α)(z)·m _(α) ₃ (z)  (1)

Here, m_(α)(z) is a primitive polynomial also serving as a modularpolynomial of the considered Galois field. α is a primitive element ofthe Galois field and root of the polynomial. The polynomial m_(α) ₃ (z)is the minimal polynomial of the root α³. The associated Galois field isdesignated by GF(2^(M)). The length of the unshortened BCH code is then2^(M)−1. If the overall parity is considered, G(z) may be represented inthe following form.

G(z)=m _(α)(z)·m _(α) ₃ (z)·(z+1)  (2)

Without integrating the overall parity, the check matrix may berepresented in its separated form as

$\begin{matrix}{H_{BCH}^{sep} = {\begin{pmatrix}\alpha^{2^{M} - 2} & \ldots & \alpha^{i} & \ldots & \alpha^{1} & \ldots & \alpha^{0} \\\alpha^{3 \cdot {({2^{M} - 2})}} & \ldots & \alpha^{3 \cdot i} & \ldots & \alpha^{3 \cdot 1} & \ldots & \alpha^{0}\end{pmatrix} = \begin{pmatrix}H_{1} \\H_{3}\end{pmatrix}}} & (3)\end{matrix}$

wherein α is a primitive element of the Galois field GF(2^(M)) and theexponents of a are each to be interpreted modulo 2^(M)−1. The parity maybe included in the error detection by selecting the check matrix as

$\begin{matrix}{H_{BCH}^{sep} = {\begin{pmatrix}\alpha^{2^{M} - 2} & \ldots & \alpha^{i} & \ldots & \alpha^{1} & \ldots & \alpha^{0} \\\alpha^{3 \cdot {({2^{M} - 2})}} & \ldots & \alpha^{3 \cdot i} & \ldots & \alpha^{3 \cdot 1} & \ldots & \alpha^{0} \\1 & \ldots & 1 & \ldots & 1 & \ldots & 1\end{pmatrix} = \begin{pmatrix}H_{1} \\H_{3} \\P\end{pmatrix}}} & (4)\end{matrix}$

wherein in the last row there are only ones.

A 1-bit error in the i-th bit position is described as [i], an L-biterror in the positions i₁, i₂, . . . , i_(l) as [i₁, i₂, . . . , i_(L)].To each error [i₁, . . . , i_(L)] an n-component error vector e(i₁, . .. , i_(L))=(e₀, . . . , e_(n−1)) is associated, wherein

$e_{i} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} i} \in {{\left\{ {i_{1},\ldots \mspace{14mu},i_{L}} \right\} L} \geq 0}} \\0 & {else}\end{matrix} \right.$

The component e_(j) of the error vector e[i₁, . . . , i_(L)] is equal to1 exactly when the corresponding j-th bit is faulty.

To an error [i_(l), . . . , i_(L)] with the error vector e=e[i₁, . . . ,i_(L)] an error syndrome

$S = {{H_{BCH}^{sep} \cdot ^{T}} = {{\begin{pmatrix}H_{1} \\H_{3}\end{pmatrix} \cdot ^{T}} = \begin{pmatrix}s_{1} \\s_{3}\end{pmatrix}}}$ with s₁ = H₁ ⋅ ^(T)  and  s₃ = H₃ ⋅ ^(T)

is associated.

By deleting columns and by reordering columns of the check matrixH_(BCH) ^(sep), a shortened BCH-code is obtained which is adapted to arequired word width.

If the parity is not considered, the code distance is 5 and if theparity is considered, the code distance is 6. Then, 1-bit errors and2-bit errors may be corrected using the syndrome. The syndromes of all3-bit errors, parity included, are different from the syndromes of all1-bit and 2-bit errors, but they may be the same among themselves.

The encoding of a BCH-code and a shortened BCH-code as a special linearcode may be done with the help of a generator matrix and the decodingwith the help of a check matrix. The connection between the generatorpolynomial and generator matrix and H-matrix is, for example, describedin Lin, S. and Costello, D.: Error Control Coding, Prentice-Hall, 1983,p. 92-95”.

In the following, the inventive concept is described by some general andsome detailed embodiments.

FIG. 1 shows a block diagram of an apparatus 100 for correcting at leastone bit error within a coded bit sequence 102 according to an embodimentof the invention. The apparatus 100 comprises an error syndromegenerator 110 connected to a bit error corrector 120. The error syndromegenerator 110 determines an error syndrome 112 of a coded bit sequence102 derived by a multiplication of a check matrix H with the bitsequence 102. The check matrix H comprises a first sub-matrix H^(u), asecond sub-matrix H^(a) and a third sub-matrix H^(c). Each sub-matrixcomprises a plurality of lines and each line comprises a plurality ofbinary components. At least a first predefined component or a secondpredefined component of each line of the first sub-matrix H^(u)comprises a first bit value (1 or 0). In other words: If the firstpredefined component and the second predefined component of a line ofthe submatrix H^(u) are equal to 0,0, then the first and the secondcomponent of any line of H^(u) are unequal 1,1, and if the firstpredefined component and the second predefined component of thesubmatrix H^(u) are equal to 1,1, then the first and the secondcomponent of any line of H^(u) are unequal 0,0.

Further, the second sub-matrix H^(a) comprises lines being linearlyindependent from each other (i.e. each line of the second sub-matrix islinearly independent from each other line of the second sub-matrix) andthe first predefined component and the second predefined component ofeach line of the second sub-matrix H^(a) comprises a same second bitvalue (0 or 1) which is different from the first bit value. The thirdsub-matrix H^(c) comprises lines being linearly independent from eachother and the first predefined component or the second predefinedcomponent of each line of the third sub-matrix H^(c) comprises the firstbit value (1 or 0).

An XOR-sum of the first predefined components of all lines of the firstsub-matrix H^(u) and the third sub-matrix H^(c) is equal to the secondbit value 0 and the XOR-sum of the second predefined components of alllines of the first sub-matrix H^(u) and the third sub-matrix H^(c) isequal to the second bit value 0. Additional results of a multiplicationof the check matrix H and a test vector is equal to a result of amultiplication of the second sub-matrix H^(a) and a resulting vector,wherein at least one component of the resulting vector comprises thesecond bit value (0 or 1). Further, the bit error corrector 120 correctsa bit error within the coded bit sequence 102 based on the determinederror syndrome 112 of the coded bit sequence 102 to obtain a correctedbit sequence 122.

By using an error syndrome 112 derivable by a check matrix describedabove, an error correction circuit for 1-bit and 2-bit errors can berealized, which is able to detect also the errors All-0 and All-1, forexample. In other words, the apparatus 100 enables to differentiateevery 1-bit error from errors All-1 and All-0. Thus, for example, it maynot be the case anymore that a word read out of a storage in case of acorrectable 1-bit error is mixed up with an All-0 or All-1 error. Thedetection and/or correction of All-0 and All-1 errors is of highinterest, because these failures are very common.

The first bit value and the second bit value may be logical 0 or logical1, or a high level or a low level of a signal in the circuitry.Therefore, there are two possible cases. Either the first bit value isequal to 1 (logical 1) and the second bit value is equal to 0 (logical0) or the first bit value is equal to 0 and the second bit value isequal to 1. Both cases represent equivalent implementations of thedescribed concept.

Further, a line of a matrix may be a row or a column of a matrix. Sincea matrix is easy to transpose, the inventive concept can be realizedindependent from whether a line of a matrix is a row or a column.Therefore, there are again two possible cases. Either each mentionedline of a matrix is a column of the respective matrix and the samecomponents (e.g. first predefined components or second predefinedcomponents) of each line of a matrix represents a row of this matrix.Otherwise each line of a matrix is a row of the respective matrix andthe same components of the lines of a matrix represent a column of thismatrix.

Consequently, in connection with the described concept, of each line ofthe first sub-matrix, of the second sub-matrix and of the thirdsub-matrix is a column of the respective sub-matrix. The firstpredefined components of the lines of the first sub-matrix H^(u), of thesecond sub-matrix H^(a) and of the third sub-matrix H^(c) represent arow of the check matrix H and the second predefined components of thelines of the first sub-matrix H^(u), of the second sub-matrix H^(a) andof the third sub-matrix H^(c) represent another row of the check matrixH. Alternatively, each line of the first sub-matrix H^(u), of the secondsub-matrix H^(a) and of the third sub-matrix H^(c) is a row of therespective sub-matrix. The first predefined components of the lines ofthe first sub-matrix H^(u), of the second sub-matrix H^(a) and the thirdsub-matrix H^(c) represent a column of the check matrix H and the secondpredefined components of the lines of the first sub-matrix H^(u), of thesecond sub-matrix H^(a) and of the third sub-matrix H^(c) representanother column of the check matrix H.

Each line of a matrix comprises a plurality of binary components. Inother words, each component is either equal to 1 or equal to 0. In thisconnection, a first predefined component and a second predefinedcomponent may be actually the first and the second component of a line,but they can also be arbitrary other components (e.g. the last and thenext to last component or the third component and the fifth component oranother predefined component combination). However, the first predefinedcomponent of the first sub-matrix, the second sub-matrix and the thirdsub-matrix are the same components within the lines of the respectivematrix, which is accordingly valid for the second predefined componentsof the lines of the first sub-matrix, the second sub-matrix and thethird sub-matrix. For example, if the first predefined component is then-th component of a line of the first sub-matrix, then the firstpredefined component of a line of the second sub-matrix means also then-th component of the line. Same is valid for the third sub-matrix aswell as for the whole check matrix.

The check matrix may also be called parity-check matrix.

For example, the check matrix may be represented in a separated form.Further, the check matrix may be a check matrix of a shortened Hammingcode, a shortened Hsiao-code or a shortened BCH-code, for example.

The error syndrome generator 110 may determine the error syndrome 112 bymultiplying the check matrix with the coded bit sequence 102.Alternatively, the error syndrome generator 110 may comprise a storagecontaining a look-up table. This look-up table may contain informationabout error syndromes corresponding to different coded bit sequences102. In other words, the look-up table may contain for each possiblecoded bit sequence the corresponding error syndrome derived by amultiplication of the check matrix with the coded bit sequence 102. Inthis example, the error syndrome generator 110 may easily determine theerror syndrome 112 by taking the stored error syndrome associated withthe coded bit sequence 102.

The error syndrome generator 110, the bit error corrector 120 and/orother optional elements described later on may be independent hardwareunits or part of a computer or microcontroller as well as a computerprogram or a software product for running on a computer ormicrocontroller.

The error syndrome generator 110, the bit error corrector 120 and/orother optional components described later on may be implementedindependent from each other or at least partly together. For this, forexample, the functionality of the error syndrome generator 110, the biterror corrector 120 and/or other optional components described below maybe at least partly united to a combined hardware unit or software unitby a synthesis tool.

During a multiplication of the check matrix H with the coded bitsequence 102, a first group of bits of the coded bit sequence 102 ismultiplied with the first sub matrix, a second group of bits of thecoded bit sequence is multiplied with the second sub-matrix and a thirdgroup of bits of the coded bit sequence is multiplied with the thirdsub-matrix. In other words, the error syndrome of the coded bit sequenceis derived based on a multiplication of the first sub-matrix with afirst group of bits of the coded bit sequence, a multiplication of thesecond sub-matrix with the second group of bits of the coded bitsequence, and a multiplication of the third sub-matrix with a thirdgroup of bits of the coded bit sequence.

In some embodiments of the invention, the first group of bits mayrepresent information bits, the second group of bits may representaddress bits and the third group of bits may represent check bits.Therefore, the first group of bits may also be called information bitsor payload data bits or useful data bits, the second group of bits maybe called address bits and the third group of bits may be called checkbits.

For example, the coded bit sequence or part of the coded bit sequencemay be stored by an addressable storage, also called a storage unit,memory or memory unit (e.g. read only memory, random access memory ornon volatile memory).

The first group of bits (data bits) may be independent from the secondgroup of bits (address bits). Therefore, only the first group of bitsand the third group of bits of the coded bit sequence may be stored atan address of the addressable storage indicated by the second group ofbits. Alternatively, the coded bit sequence may also be coded by aninner code, so that at least one bit of the first group of bits dependson at least one bit of the second group of bits.

In the following, an embodiment of the invention is described in moredetail. In this example, the lines of the matrices are columns, thefirst predefined components of the lines of the matrices represent thefirst row of the matrices, the second predefined components of the linesof the matrices represent the second rows of the matrices, the first bitvalue is equal to 1 and the second bit value is equal to 0. If thedescription of the detailed embodiment several additional and/oroptional features can be implemented all together or one or some of themmay be implemented independent from the other features described.

It is illustrated in FIG. 2 how the addresses a=a₁, . . . a_(l) (e.g.provided by an address generator 13) are to be considered in the encodedstoring of the payload data bits u=u₁, . . . , u_(k). At the encoder (orcoder) 11 k bits wide payload data u=u₁, . . . , u_(k) and the l bitwide address a=a₁, . . . a_(l) at which the storage 12 is to be written,are applied, so that the address a is also applied to the address inputof the storage 12. The coder 11 forms the k+l+m bit wide code word v(coded bit sequence) from the payload data u (information bits) and theaddress a (address bits),

v=(u,a)·G

In the storage 12 under the address a the code word v is stored, whosebits depend both on the payload data (information bits) and also on theaddress (address bits). If the generator matrix is used in itssystematic form

G=(I _(k+1) ,P _(k+Lm))

The code word v has the form v=u, a, c and the check bits c added to thepayload data bits and the address bits are designated by

c=(u,a)·P,

while the payload data bits u and the address bits a, are not modifiedin this example. I_(k+l) is the (k+l) dimensional identity matrix and Pis a (k+l,m) matrix determining the test equations of the code.

The encoding including the address bits for a generator matrix in thesystematic form is illustrated in FIG. 3. In the storage 22 (addressablestorage) only the data bits u and the check bits c are stored, while theaddress bits a do not have to be stored. The check bits c here bothdepend on the data bits u and also on the address bits a. The addressbits generated by the address generator 23 are applied to the addressinput of the storage 22 and to the corresponding first inputs of theencoder (or coder) in a systematic form 21, while at the second k bitwide input of the coder the payload data bit u are applied, which aresimultaneously also applied to the first k bits wide data input of thestorage 22. The coder generates, at its m-bit wide output, the checkbits c, which are applied to the second m bit wide data input of thestorage 22.

FIG. 4 shows a circuitry for generating a syndrome S=(s₁, s₃) for a2-bit error correcting shortened BCH-code according to an embodiment.The bits u′ and c′ stored in the storage 32 (addressable storage) areoutput from the storage 32 under the address a′ provided by the addressgenerator 33. The address generated by the address generator here hasthe word width l−1. The data, the address and the check bits aredesignated in FIG. 4 by u′, a′, c′ to indicate that the correspondingbits may be erroneously changed. The data bits u′ are supplied into afirst input 311 of the word width k, the check bits c′ are supplied intoa second input 312 and the address bits a′ are supplied into a thirdinput 313 of the word width l−1 of the syndrome generator 31. At afourth 1 bit wide input 314 the constant value 1 is applied. Thesyndrome generator 31 may be a combinatorial circuit determined by thecheck matrix. It serves for forming the syndrome S=(s₁, s₃) of theconsidered BCH code determined as a column vector S^(T) with respect to

S ^(T)=(s ₁ ,s ₃)^(T)=(S ₁ ,S ₂ , . . . ,S _(m))^(T) =H·(u′ _(l) , . . .,u′ _(k) a′ _(l) , . . . ,a′ _(l) ,c′ _(l) , . . . ,c′ _(m))^(T).

The address bits a₁′, . . . , a′_(l−1) provided by the address generatorand the constant value 1 form, as described in detail later, the addressbits a′₁, . . . , a′_(l). The check matrix H of the shortened BCH-codeconsists of a first (m,k) sub-matrix H^(u), a second (m,l) sub-matrixH^(a) and a third (m,m) sub-matrix H^(c), wherein the first k columns ofthe check matrix H form the sub-matrix H^(u), the subsequent l columnsform the sub-matrix H^(a) and the last m columns the sub-matrix H^(c). Asub-matrix may also be called a partial matrix. The following applieshere:

${H^{u} = {\begin{pmatrix}h_{1,1}^{u} & \ldots & h_{1,k}^{u} \\\vdots & \vdots & \vdots \\h_{m,1}^{u} & \ldots & h_{m,k}^{u}\end{pmatrix} = \left( {h_{1}^{u},\ldots \mspace{14mu},h_{k}^{u}} \right)}},{H^{a} = {\begin{pmatrix}h_{1,1}^{a} & \ldots & h_{1,l}^{a} \\\vdots & \vdots & \vdots \\h_{m,1}^{a} & \ldots & h_{m,l}^{a}\end{pmatrix} = \left( {h_{1}^{a},\ldots \mspace{14mu},h_{l}^{a}} \right)}},{H^{c} = {\begin{pmatrix}h_{1,1}^{c} & \ldots & h_{1,m}^{c} \\\ldots & \ldots & \ldots \\h_{m,1}^{c} & \ldots & h_{m,m}^{c}\end{pmatrix} = \left( {h_{1}^{c},\ldots \mspace{14mu},h_{m}^{c}} \right)}}$

For the components S₁, S₂, . . . , S_(m) of the syndrome S=(S₁, . . . ,S_(m))=(s₁, s₃) applies

(s ₁ ,s ₃)^(T)=(S ₁ , . . . ,S _(m))^(T)=(H ^(u) ,H ^(a) ,H ^(c))·(u′ ₁, . . . ,u′ _(k) ,a′ ₁ , . . . ,a′ _(l) ,c′ ₁ , . . . ,c′ _(m))^(T),

and the syndrome generator 31 realizes at its m outputs for i=1, . . . ,m the Boolean functions

S _(i) =h _(i,j) ^(u) u′ ₁ ⊕ . . . ⊕h _(i,k) ^(u) u′ _(k) ⊕h _(i,l) ^(u)a′ ₁ ⊕ . . . ⊕h _(i,l) ^(a) a′ _(l) ⊕h _(i,l) ^(c) c′ ₁ ⊕ . . . ⊕h_(i,m) ^(c) c′ _(m)

which are uniquely determined by the elements h_(i,j) ^(u), h_(i,j)^(a), h_(i,j) ^(c) of the sub-matrices H^(u), H^(a), H^(c). A concreteimplementation, e.g. by XOR-gates, is easy realizable, so that theproposed syndrome generator is easily described by the concrete form ofthe matrices H^(u), H^(a), H^(c).

The matrices H^(u), H^(a), H^(c) are determined by deleting certaincolumns and by reordering columns from the columns of the (m,2^(M)−1)check matrix H_(unverk) ^(BCH) of an unshortened 2-bit error correctingBCH-code of length 2^(M)−1 such that m+l+k<2^(M)−1. Here, the checkmatrix of the unshortened code is selected in its separated form, forexample. The matrix H_(unverk) ^(BCH) then has the following form

$H_{unverk}^{BCH} = {\begin{pmatrix}H_{1} \\H_{3}\end{pmatrix}.}$

As the i-th column of the matrix H₁ is determined by α^(i), i=0, . . . ,2^(M)−2 and α is a primitive element of the Galois field GF(2^(M)), all2^(M)−1 M-digit binary vectors, except for 0, occur as columns of H₁.Now a j-th component and a k-th component of the first M components ofthe check matrix are selected, wherein j≠k. The j-th component isdesignated as the first (selected) component (first predefinedcomponent) and the k-th component as the second (selected) component(second predefined component).

As a is a primitive element of the Galois field GF(2^(M)), and all2^(M)−1 possible m-digit binary vectors occur as columns of the checkmatrix H₁, there are for each of the values 01, 10 and 11 2^(M−2)columns of the check matrix H₁ taking on the value 01, 10 and 11 in thetwo selected components (predefined components). Apart from that, thereare 2^(M−2)−1 columns of the matrix H₁ taking on the value 00 in the twoselected components. All columns of the check matrix H_(unverk) ^(BCH)are classified into four disjoint sets Sp⁰⁰, Sp¹⁰, Sp⁰¹ and Sp¹¹,wherein Sp⁰⁰ contain all 2^(M−2)−1 columns with the first two components00, Sp¹⁰ all 2^(M−2) with the first two components 10, Sp⁰¹ all 2^(M−2)columns with the first two components 01 and Sp¹¹ all 2^(M−2) columnswith the first two components 11.

According to the described concept, l linearly independent columns h₁^(a), . . . , h_(l) ^(a) form the matrix H^(a)

H ^(a)=(h ₁ ^(a) , . . . , h _(l) ^(a)),

wherein h_(j) ^(a)εSp⁰⁰ applies.

As the first two components of Sp⁰⁰ are equal to 00 (first predefinedcomponent and second predefined component of each line of the firstsub-matrix comprises the same second bit value), there are m−2 linearlyindependent columns, and l≦m−2 applies. For l=m−2, the (l, l) matrix{tilde over (H)}^(a), resulting from H^(a),by deleting the first twolines (which say 0, . . . 0) may be invertible.

In other words, a number of bits of the second group of bits of thecoded bit sequence may be smaller than or equal to a number of bits ofthe third group of bits of the coded bit sequence minus 2.

The columns of the matrix H^(c),

H=(h ₁ ^(c) , . . . ,h _(m) ^(c)),

are selected so that they are linearly independent and that their firsttwo components (first predefined component and second predefinedcomponent) are unequal 00 (first predefined component or secondpredefined component of each line of the third sub-matrix comprises thefirst bit value), so that for i=1, . . . , m the following applies

h_(i) ^(c)ε{Sp¹⁰∪Sp⁰¹∪Sp¹¹}

The columns of the matrix H^(c) form the set Sp^(H) ^(c) ={h₁ ^(c), . .. , h_(m) ^(c)}.

The columns of the matrix H^(u),

H ^(u)=(h ₁ ^(u) , . . . ,h _(k) ^(u)),

are selected so that the first two components are unequal 00 (firstpredefined component or second predefined component of each line of thesecond sub-matrix comprises the first bit value), so that for i=1, . . ., k the following applies

h _(i) ^(u) ε{Sp ¹⁰ ∪Sp ⁰¹ ∪Sp ¹¹ }\SP ^(H) ^(c)

In other words, the lines (in this example, the columns) of the firstsub-matrix are all different from the lines of the third sub-matrix.

In addition to that, the columns of the matrices H^(u), H^(a), H^(c) aredetermined so that the following applies:

-   -   1. The XOR-sum at the first components of all columns is equal        to 0 (second bit value).    -   2. The XOR-sum at the second components of all columns is equal        to 0.    -   3. The l-dimensional binary vector a″₁, . . . , a″_(l)        (resulting vector), determined by

$s_{{All}\; 1} = {{\left( {H^{u},H^{c}} \right)\underset{\underset{k + m}{}}{\cdot \left( {1,\ldots \mspace{14mu},1} \right)^{T}}} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{l}^{''}} \right)^{T}}}$

-   -   -   has at least one component a″_(i)=0, iε{1, . . . , l} (at            least one component of the resulting vector comprises the            second bit value). The vector (1, . . . , 1)^(T) to be            multiplied with the sub-matrix H^(u) and the sub-matrix            H^(c) may also be called a test vector. Alternatively, the            test vector is multiplied with the whole check matrix. For            this, the test vector comprises zeros for bits multiplied            with components of lines of the second sub-matrix H^(a).

In other words, each component of the test vector being multiplied withthe component of a line of the first sub-matrix and of the thirdsub-matrix comprises the first bit value and each component of the testvector being multiplied with a component of a line of the secondsub-matrix comprises the second bit value.

In the following it is to be described how the matrices H^(u), H^(a),H^(c) of the inventive syndrome generator may be determined practically.

From the sets Sp¹⁰, Sp⁰¹ and Sp¹¹, the sets Spe¹⁰, Spe⁰¹, Spe¹¹ areformed by deleting two random columns each and summarizing the deletedcolumn into the sets Sp2¹⁰, Sp2⁰¹ and Sp2¹¹. z Thus, the set Sp2⁰¹contains the two columns which were deleted from the set Sp⁰¹ in orderto determine the set Spe⁰¹.

From the set {Spe¹⁰∪Spe⁰¹∪Spe¹¹} m linearly independent columns aredetermined, designated by h₁ ^(c), . . . h_(m) ^(c) and which form thematrix (third sub-matrix)

H ^(c)=(h ₁ ^(c) , . . . , h _(m) ^(c)).

As a set, these columns are combined into the set Sp^(H) ^(c) ={h₁ ^(c),. . . , h_(m) ^(c)}.

From the set Sp⁰⁰ l columns are determined which are linearlyindependent. These columns are designated by h₁ ^(a), . . . , h_(l) ^(a)and they form the matrix (second sub-matrix)

H ^(a)=(h ₁ ^(a) , . . . , h _(l) ^(a)).

The matrix H^(u) (first sub-matrix) consists of k columns h_(l) ^(u), .. . , h_(k) ^(u), wherein

h _(i) ^(u) ε{Spe ¹⁰ ∪Spe ⁰¹∪Spe¹¹ }\SP ^(H) ^(c)

apply and wherein at least one column from Spe¹⁰, at least one columnfrom Spe⁰¹ and at least one column from Spe¹¹ is contained in {h₁ ^(u),. . . , h_(k) ^(u)}.

Thus, H^(u) contains at least one column whose first two components areequal to 10, at least one column whose first two components are equal to01 and at least one column whose first two components are equal to 11.

More general, the first sub-matrix comprises at least one line with thefirst predefined component being equal to the first bit value and thesecond predefined component being equal to the second bit value, atleast one line with the first predefined component being equal to thesecond bit value and the second predefined component being equal to thefirst bit value and at least one line with the first predefinedcomponent and the second predefined component being equal to the firstbit value.

Now, the XOR-sum of the first and the second components of the columnsof H^(u) and H^(c) are determined. Depending on the value of thisXOR-sum, the following four cases are considered:

-   -   1. If the XOR-sum is (1,1), one column of H^(u) whose first two        components are equal to (0,1), are replaced by a column of        Sp2¹⁰. Then, the XOR-sum of the first two components of the        columns of H^(u), H^(c), after this replacement, is equal to        (0,0).    -   2. If the XOR-sum is equal (0,1), a column of H^(u) is replaced        whose first two components are equal to (1,0), by a column from        Sp2¹¹. Then, the XOR-sum of the first two components of the        columns of H^(u), H^(c), after this replacement, are equal to        (0,0).    -   3. If the XOR-sum is equal to (1,0), a column of H^(u) whose        first two components are equal to (0,1) is replaced by a column        of Sp2¹¹. Then the XOR-sum of the first two components of the        columns of H^(u), H^(c) after this replacement are equal to        (0,0).    -   4. If the XOR-sum is equal to (0,0), then in this step no        modification is executed.

From the matrices H^(u) and H^(c) obtained so far, now the vector a″₁, .. . , a″_(l) is determined by solving the linear equation system

${\left( {H^{u},H^{c}} \right) \cdot \left( \underset{\underset{k + m}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{l}^{''}} \right)^{T}}$${\left( {H^{u},H^{c}} \right) \cdot \left( \underset{\underset{k + m}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} = {H^{a} \cdot {\left( {a_{1}^{\prime},\ldots \mspace{14mu},a_{l}^{\prime}} \right).}}$

If i, 1≦i≦l so that a″_(i)=0, then by the check matrix H=(H^(u) H^(a)H^(c)) determined so far, the syndrome generator is determined. At theinput 314 of FIG. 4 then the value 1 for the i-th address bits a″_(i)=1is input as being constant. If there is no i, 1≦i≦l, so that a″_(i)=0,the following applies

$a_{1}^{\prime},\ldots \mspace{14mu},{a_{l}^{\prime} = {\underset{\underset{l}{}}{1,\ldots \mspace{14mu},1}.}}$

Then, in H^(u) a column h_(j) ^(u) with the value of the first twocomponents (0,1) is for example replaced by a column hεSp2⁰¹ which wasnot part of H^(u) before. The matrix H^(u) modified this way isdesignated by H^(u′). The solution of the linear equation system

$\begin{matrix}{{\left( {H^{u^{\prime}},H^{c}} \right) \cdot \left( \underset{\underset{k + m}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{l}^{''}} \right)^{T}}} & (9)\end{matrix}$

then inevitably leads to a solution with

$a_{1}^{\prime},\ldots \mspace{14mu},{a_{l}^{\prime} \neq \underset{\underset{l}{}}{1,\ldots \mspace{14mu},1}},{{{{as}\left( {H^{u^{\prime}},H^{c}} \right)} \cdot \left( \underset{\underset{k + m}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} = {{\left( {H^{u},H^{c}} \right) \cdot \left( \underset{\underset{k + m}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} + h_{j}^{u} + h}}$

and h_(j) ^(u)+h≠0.

If a″₁, . . . , a″_(l) is the solution of equation (9), then after thismodification of H^(u) into H^(u′) a″_(i)=0. As illustrated in FIG. 4,then for the i-th bit of the address the constant value 1 is input asthe input 314. In other words, a bit of the second group of bitsassociated to the at least one component of the resulting vectorcomprising the second bit value comprises the first bit value.

The just determined H-matrix may then determine, for example, the XORtrees implementing the syndrome generator. In this example, the syndromegenerator has, for example, the following advantageous characteristics:

-   -   1. For any address a₁, . . . , a_(i−l)a_(i)=1, a_(i+1) . . . ,        a_(l) and for u=0, . . . ,0 and c=0, . . . ,0 or u=1, . . . ,1        and c=1, . . . ,1 there is no code vector of the shortened        BCH-code. The errors “All-0” and “All-1” may thus never be code        vectors of the shortened BCH-code, whereby they be detected        relatively easily.        -   For example, this characteristic is achieved in particular            by the value of a certain address bit constantly being equal            to 1, that the columns of the matrix H^(a) being linearly            independent, that the XOR-sum of the first and the second            components of the columns of the matrices H^(u) and H^(c)            being equal to 0 and that the first and the second            components of all columns of the matrix H^(a) being equal to            0.    -   2. A word comprising exactly a single 1 in the data bits u or        the check bits c may never be a code word.        -   As the first two components of the columns of H^(u) and the            columns of H^(c)≠00 and the first two components of H^(a)            being (0,0), the first two components S₁, S₂ of the syndrome            S for a 1-bit error in the data bits or check bits are            always unequal to 00, and no code word may be present. Thus,            it is not possible either for a code word being corrupted by            a 1-bit error in “All-0”.    -   3. A word comprising exactly a single 0 in the data bits u or        the check bits c may never be a code word.        -   As the first two components of the columns of H^(u) and the            columns H⁰≠(0,0), and the XOR-sum of these components of all            columns of the matrices H^(u) and H^(c) equal (0,0), and the            first two components of H^(a) are equal to (0,0), the first            two components S₁, S₂ of the syndrome S are always unequal            00 and no code word may exist. Thus, it is not possible            either for a code word to be corrupted by a 1-bit error in            “All-1”.

The concept described for determining a syndrome generator bydetermining its check matrix may be generalized relatively easily, iffurther conditions regarding columns of the check matrix are to befulfilled. As an example of such a condition the case is regarded thatin each column of the check matrix the number of ones in a subset ofcomponents (predefined plurality of components) of the column is odd. Inother words, an XOR-sum of a predefined plurality of components of eachline of the check matrix H is equal to a same bit value. As an examplefor such a subset, here the lower N components of each column areregarded belonging to the matrix H₃. The number of ones in the lower Ncomponents thus is to be odd. If this condition is fulfilled, the parityP may be determined as an XOR-sum via the components of the sub-syndromes₃, which may be done by an XOR tree with only N inputs. For thedetermination of the overall parity from the data bits, the address bitsand the check bits, however, an XOR tree with n inputs is required,wherein n is the length of the code.

For example, for a parity bit a row may be added to the check matrixcomprising only ones. In other words, a predefined same component of alllines of the check matrix may comprise a same bit value.

From the columns of the check matrix H_(unverk) ^(BCH) with 2^(M)−1columns, the columns of this matrix are determined fulfilling therequired condition. It is here the columns comprising an odd number ofones in the N bottom components. Depending on whether the first twocomponents of these columns are 00, 10, 01 or 11, these columns areassociated to the set Sp*⁰⁰, Sp*¹⁰, Sp*⁰¹ and Sp*¹¹.

Based on these sets Sp*⁰⁰, Sp*¹⁰, Sp*⁰¹ and Sp*¹¹ just as described forthe set Sp⁰⁰, Sp¹⁰, Sp⁰¹ and Sp¹¹, a check matrix H*=(H*^(u), H*^(a),H*^(c)) and thus a syndrome generator may be determined, so that thecolumns of its check matrix H* comprise an additional characteristic.Here it is the characteristic that the bottom N components comprise anodd number of ones.

A concrete example is described for N=7 and the Galois field GF(2⁷). Asa modular polynomial, the primitive polynomial m_(α)=z⁷+z³+1 is used,for example, indicated in

“Peterson, W., and Weldon, E.: Error Correcting Codes, 2. Auflage, MITPress, 1972, Annex C, S. 476”. The length of the unshortened code isn=2⁷−1=127. The H-matrix of the unshortened BCH-code for the 2-bit errorcorrection then is

$\begin{matrix}{{H_{BCH}^{sep} = \begin{pmatrix}\alpha^{126} & \ldots & \alpha^{2} & \alpha^{1} & \alpha^{0} \\\alpha^{\alpha \cdot 126} & \ldots & \alpha^{3 \cdot 2} & \alpha^{3 \cdot 1} & \alpha^{0}\end{pmatrix}},} & (10)\end{matrix}$

wherein the exponents j of a′ are to be regarded as modulo 127, so thatfor example the exponent 3·126 means (3·126) modulo 127=124. The valuesα^(i) and α^(3i) in the column α^(i), α^(3i) are initially illustratedin the vector illustration as 2 seven digit binary vectors, combinedinto a 14-digit binary vector and regarded as a 14-digit binary number.This 14 digit binary number may be represented as a decimal number.

The following applies

(α⁰,α⁰)=(00000010000001)_(bin)=129

(α¹,α³)=(00000100001000)_(bin)=264

(α²,α⁶)=(00001001000000)_(bin)=576

Wherein the 129 is the decimal value for the first column, 264 is thedecimal value for the second column and 576 is the decimal value for thethird column.

Here, the left most bit is the first bit and the right most bit is thefourteenth bit. The first bit and the second bit are underlined. Theseare the bits whose XOR-sum across all columns of the check matrix of theshortened BCH-code are 0,0. The columns of the unshortened H-matrix arethen given by the following decimal numbers.

129, 264, 576,1060, 2098, 4107, 8280, 1261, 2398, 4701, 9285, 3212,6496, 12854, 8363, 1482, 2932, 5663, 11377, 7351, 14627, 13962, 10704,6061, 12154, 6895, 13646, 11988, 6541, 13160, 8950, 399, 888, 1663,3143, 6172, 12393, 9470, 3535, 7004, 13901, 10444, 5572, 11012, 4768,9490, 3737, 7489, 14892, 12530, 9647, 4074, 8038, 15878, 14512, 13723,12241, 7077, 14138, 10955, 4604, 9055, 725, 1285, 2600, 5202, 10301,5363, 10535, 5802, 11586, 7860, 15675, 16067, 14780, 14331, 11239, 5006,10096, 2751, 5475, 10798, 4322, 8486, 1698, 3330, 6672, 13321, 11464,7652, 15126, 12985, 8659, 1973, 3891, 7683, 15384, 15561, 15852, 16342,15261, 13281, 9150, 1003, 1902, 3654, 7188, 14377, 13530, 11773, 8151,16149, 15009, 12698, 10201, 3045, 5918, 11897, 6391, 12551, 9912, 2523,4981, 9751, 2225, 4371, 8721

Based on these 127 columns, now the sets Sp⁰⁰, Sp¹⁰, Sp⁰¹ and Sp¹¹ areformed, whose first two components in binary representation are 00, 10,01 and 11. Thus, for example the columns 129, 264 and 576 are part ofset Sp⁰⁰, as the first two components of these numbers are equal to 00in a binary representation.

Based on the sets Sp⁰⁰, Sp¹⁰, Sp⁰¹ and Sp¹¹, the sets Sp*⁰⁰, Sp*¹⁰,Sp*⁰¹ and Sp*¹¹ are determined by the additional condition that thecolumns of the check matrix in their binary representation in the bits8-14 comprise an odd number of ones. Thus, the columns 1, 2 and 3 (129,264, 567) belong to Sp*⁰⁰, as these columns belong to Sp⁰⁰ and inaddition to that comprise, in the bits 8-14 one 1 each, i.e. an oddnumber of ones.

The following applies:

Sp*⁰⁰={129, 264, 576, 2098, 1261, 2398, 1482, 1663, 3535, 3737, 3330,1003, 1902, 3654, 2523, 2225}

Sp*¹⁰={8280, 9285, 12154, 11988, 8950, 10444, 11012, 9647, 12241, 10301,11239, 100%, 8486, 9150,11897,9912}

Sp*⁰¹={4107, 4701, 5663, 7351, 6541, 6172, 4768, 7077, 4604, 5202, 5363,5802, 7860, 5006, 4322, 6672, 7652, 8151, 4981, 4371}

Sp*¹¹={14627, 13160, 14892, 15675, 16067, 15126, 15561, 13281, 14377,16149, 12698, 12551}.

From the set Sp*¹⁰, the set Spe¹⁰ is formed, by removing the two columns9647, 12241 and combining these two columns into the set Sp2¹⁰={9647,12241}. The following applies.

Spe¹⁰={8280, 9285, 12154, 11988, 8950, 10444, 11012, 10301, 11239,10096, 8486, 9150, 11897, 9912}.

From the set Sp*⁰¹, the set Spe⁰¹ is formed, by removing the two columns7077, 4604 and combining these two columns into the set Sp2⁰¹={7077,4604}. The following applies:

Spe⁰¹={4107, 4701, 5663, 7351, 6541, 6172, 4768, 5202, 5363, 5802, 7860,5006, 4322, 6672, 7652, 8151, 4981, 4371}.

From the set Sp*¹¹, the set Spe¹¹ is formed, by removing the two columns16149, 13281 and combining these two columns into the set Sp2¹¹={16149,13281}. The following applies:

Spe¹¹={14627, 13160, 14892, 15675, 16067, 15126, 15561, 14377, 12698,12551}.

From the set Sp*⁰⁰, m−2=14−2=12 linearly independent vectors areselected forming the matrix H^(a). The following applies:

H^(a)=(129, 264, 576, 2098, 1261, 2398, 1482, 3737, 3330, 1003, 3654,2225).

From the set Spe¹⁰∪Spe⁰¹∪Spe¹¹ 14 linearly independent columns aredetermined forming the matrix H^(c). The following applies:

H^(c)=(8280, 4107, 6672, 9285, 4768, 11012, 6172, 5202, 8486, 4371,4322, 10444, 12551, 14377).

These columns form the set Sp^(H) ^(c) , wherein

Sp^(H) ^(c) ={8280, 4107, 6672, 9285, 4768, 11012, 6172, 5202, 8486,4371, 4322, 10444, 12551, 14377}.

From the set {Spe¹⁰∪Spe⁰¹∪Spe¹¹}\sp^(H) ^(c) 16 vectors are selectedforming the columns of H^(u). These columns are determined so that theycontain at least one vector from Spe¹⁰, one vector from Spe⁰¹ and onevector from Spe¹¹. Temporarily, the matrix H^(u) results with

H^(u)=(4701, 14627, 6541, 13160, 14892, 10301, 5802, 5006, 10096, 12698,9912, 5663, 11988, 8950, 15675, 7351).

For the XOR-sum of the first two components of the columns of H^(u) andH^(c) the value 10 results. To obtain a value 00 for this sum, a columnwith the first two components 01 is replaced by a column with the firsttwo components 11 of Spe¹¹, so that the XOR-sum now is 00. Concretely,column 7351 is replaced by column 16149 of Spe¹¹. The matrix H^(u) isnow:

H^(u)=(4701, 14627, 6541, 13160, 14892, 10301, 5802, 5006, 10096, 12698,9912, 5663, 11988, 8950, 15675, 16149)

From the thus determined matrices H^(u), H^(a), H^(c) now the vectora″₁, . . . , a″_(l) is determined for which

$s_{{All}\; 1} = {{\left( {H^{u},H^{c}} \right) \cdot \left( \underset{\underset{16 + 14}{}}{1\;,\ldots \mspace{14mu},1} \right)^{T}} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{12}^{''}} \right)^{T}}}$

applies.

Due to

S _(All1)=00010000110110

a″₁, . . . , a″₁₂ is determined as the solution of the linear equationsystem

s _(All1) =H ^(a)·(a″ ₁ , . . . , a″ ₁₂)^(T)

for a′₁, . . . , a′₁₂=101000000011. As e.g. a′₂=0, the syndromegenerator is determined by the just determined check matrix simply by animplementation of the corresponding linear equations with a synthesistool, for example.

The parity signal results in the presented embodiment as an XORoperation of the components of the sub-syndrome s₃, i.e. by an XORoperation of the components 8 to 14 of the syndrome S. If the conditionthat the components 8 to 14 of the check matrix contain an odd number ofones is not required, the check matrix may also be supplemented by aline consisting of all ones. In a 2-bit error correcting BCH-code, thenan odd number of check bits is obtained.

It is illustrated in FIG. 5, how the concept of the memory cells (of thestorage) regarding the error “All-1” and “All-0” may be monitored. Thepartial circuits and connections designated by the same numbers in FIG.5 and FIG. 4 have the same meaning as in FIG. 4. In addition to FIG. 4,the k bits wide output carrying the signal u′ (first group of bits,information bits) and the m bit wide output carrying the signal c′(third group of bits, check bits) of the storage 32 are supplied bothinto the k+m bit wide inputs of an NOR-gate 34 and also into the k+m bitwide input of the AND gate 35. The NOR-gate 34 outputs the valueAll-0=1, if the memory outputs the value “All-0” under any address,while the AND-gate outputs the value All-1=1, if the memory outputs thevalue All-1 under any address. As neither All-1 nor All-0 is a code wordfor any address, an All-0 error is detected at the outputs of theNOR-gate 34 by 100%, while an All-1 error is detected at the output ofthe AND-gate 35 at 100%.

More general, the NOR-gate 34 and the AND-gate 35 may also be calledsame-bit-value-detector. A same-bit-value-detector may provide a signalindicating whether or not all bits of the first group of bits and allbits of the third group of bits of the coded bit sequence comprise asame bit value (All-0 or All-1).

FIG. 6 shows an inventive syndrome generator 40 which outputs at its mbit wide output the value of the error syndrome S, the output beingconnected with the respective inputs of the circuits K₁ ^(u), K₂ ^(u), .. . , K_(k) ^(u) 41, 42, . . . 4 k (which may be part of the bit errorcorrector) for determining 1-bit wide correction values Δu₁, Δu₂, . . ., Δu_(k), which are outputted by these circuits at their respectiveoutputs and XOR-ed with the data bits u′₁, u′₂, . . . u′_(k) to becorrected. Functionally, for i=1, . . . , k for the correction values isΔu_(i):

${\Delta \; u_{i}} = {{K_{i}^{u}(S)} = \left\{ \begin{matrix}{1\mspace{14mu}} & {for} & {\mspace{14mu} {S = h_{i}^{u}}} \\{1\mspace{11mu}} & {for} & {\mspace{14mu} {S = {h_{i}^{u} + h}}} \\0 & \; & {\mspace{45mu} {else}}\end{matrix} \right.}$

Here, h_(i) ^(u) is the i-th column of the matrix H^(u) and h a columnof the matrix H^(u) or a column of the matrix H^(c), wherein h≠h_(i)^(u).

Correction circuits are for example also described in “Okamo, H. andImai, H.: A Construction Method for Decoders of BCH-Codes for BoseChaudhuri-Hocquenghem and Reed Salomon Codes, IEEE Trans. Comp. C 36, No10, pp. 1165-1171, 1985”.

FIG. 7 shows an inventive syndrome generator 40, comprising,additionally to FIG. 6, further circuits K₁ ^(c) 411, K₂ ^(c) 412, . . ., K_(m) ^(c) 41 m (which may also be part of the bit error corrector)for determining correction values Δc₁, Δc₂, . . . , Δc_(m), which areoutputted by these circuits at their outputs and that are XORed with thecheck bits component-by-component for correcting the check bits. Thecircuit parts not differing from FIG. 6 are numbered as in FIG. 6.Functionally, in the case of a 1-bit or 2-bit error, the circuit K_(j)^(c) 41 with (j=1, . . . , m) realizes the function

${\Delta \; c_{j}} = {{K_{j}^{c}(S)} = \left\{ \begin{matrix}{1\mspace{14mu}} & {for} & {\mspace{14mu} {S = h_{j}^{c}}} \\{1\mspace{11mu}} & {for} & {\mspace{14mu} {S = {h_{j}^{c} + h}}} \\0 & \; & {\mspace{45mu} {else}}\end{matrix} \right.}$

Thereby, h_(j) ^(c) is the j^(th) column of matrix H^(c) and h is acolumn of the matrix H^(u) or the matrix H^(c) with h≠h_(j) ^(c).

FIG. 8 shows an inventive syndrome generator 40, which comprises, inaddition to FIG. 7, a further circuit for determining address errors 421(which may also be part of the bit error corrector). This circuitoutputs the value E_(a)=1 at its output when a 1-bit or 2-bit addresserror has occurred. Functionally, for the circuit 421 for determiningaddress errors, the following applies

${E_{a}(S)} = \left\{ \begin{matrix}{1\mspace{14mu}} & {\mspace{14mu} {for}} & {S = h^{a}} \\{1\mspace{11mu}} & {\mspace{11mu} {for}} & {S = {h^{a} + h}} \\{0\mspace{14mu}} & {\mspace{14mu} {for}} & {S = h^{*}} \\{0\mspace{14mu}} & {\mspace{14mu} {for}} & {S = {h^{*} + h^{\prime}}} \\{0\mspace{14mu}} & {\mspace{14mu} {for}} & {S = 0} \\ - & \; & {else}\end{matrix} \right.$

wherein h^(a) is a column of matrix H^(a), h a column of the matricesH^(u), H^(a), H^(c) with h≠h^(a) and h* and h′ are columns of matricesH^(u) and H^(c) with h*≠h′.

FIG. 9 shows a specific embodiment of a circuit 421 of FIG. 8 fordetecting address errors. The circuit of FIG. 9 consists of I circuitsK₁ ^(a) 51, . . . , K_(l) ^(a) 5l for determining l correction valuesΔa₁, . . . , Δa_(l) of the possibly erroneous address bits a′₁, . . . ,a′_(l). The outputs of circuits 51, . . . , 5 l carrying the correctionvalues Δa₁, . . . , Δa_(l) are provided to the input of an OR-gate 53outputting the address error signal E_(a) at its output.

For i=1, . . . , l, for the correction value Δa_(i), the followingapplies

${\Delta \; a_{i}} = \left\{ \begin{matrix}{1\mspace{14mu}} & {for} & {\mspace{14mu} {S = h_{i}^{a}}} \\{1\mspace{11mu}} & {for} & {\mspace{14mu} {S = {h_{i}^{a} + h}}} \\0 & \; & {\mspace{45mu} {else}}\end{matrix} \right.$

Thereby, h_(i) ^(a) is the i^(th) column of matrix H^(a) and h is acolumn of matrices H^(u), H^(a), H^(c) with h≠h_(i) ^(a).

In FIG. 10, it is illustrated how for i=1, . . . , k, the outputs ofcircuits K_(i) ^(u), which are outputting a correction signal Δu_(i) forcorrecting the bit u′_(i), are connected by an OR-gate with k inputs 61to a correction signal u_(korr) ^(OR). Based on signal u_(korr) ^(OR),it can be determined easily whether a correction has taken place at allin bits u′₁, . . . , u′_(k). The outputs of circuits K_(i) ^(u), i=1, .. . , k are connected with the respective i^(th) input of the OR-gate 61outputting the signal

u _(korr) ^(OR) =Δu ₁ {circle around (+)}Δu ₂ {circle around (+)} . . .{circle around (+)}Δu _(k)

at its output.

In FIG. 11, it is illustrated how for i=1, . . . k, the outputs ofcircuits K_(i) ^(u), which are outputting a correction signal Δu_(i) forcorrecting the bit u′_(i) at its output, are connected to a correctionsignal u_(korr) ^(XOR) by an XOR-gate with k inputs 62. Based on thesignal u_(korr) ^(XOR), it can be determined easily whether an oddnumber of corrections of bits u′₁, . . . , u′_(k) has taken place. Theoutputs of circuits K_(i) ^(u), i=1, . . . , k are connected with therespective i^(th) input of the XOR-gate 62 outputting the signal

u _(korr) ^(XOR) =Δu ₁ ⊕Δu ₂ ⊕ . . . ⊕Δu _(k)

at its output.

In FIG. 12, it is illustrated how for i=1, . . . , m the outputs ofcircuits K_(i) ^(c), which are outputting a correction signal Δc_(i) forcorrecting the bits c′_(i) at their output, are connected to acorrection signal c_(korr) ^(OR) by an OR-gate with m inputs 71. Basedon the signal c_(korr) ^(OR), it can be determined easily whethercorrection has taken place at all in bits c′₁, . . . , c′_(m). Theoutputs of circuits K_(i) ^(c), i=1, . . . , m are connected to therespective i^(th) input of the OR-gate 71 outputting the signal

c _(korr) ^(OR) =Δc ₁

Δc ₂

. . .

Δc _(m)

at its output.

In FIG. 13, it is illustrated how for i=1, . . . ,m, the outputs ofcircuits K_(i) ^(c), which are outputting a correction signal Δc_(i) forcorrecting the bit c′_(i) at their output, are connected to a correctionsignal c_(korr) ^(XOR) by an XOR-gate with m inputs 72. Based on thesignal c_(korr) ^(XOR), it can be determined easily whether an oddnumber of corrections of the bits c′₁, . . . , c′_(m) has taken place.The outputs of circuits K_(i) ^(c), i=1, . . . ,m are connected to therespective i^(th) input of the XOR-gate 72, which outputs the signal

c_(korr) ^(XOR) =Δc ₁ ⊕Δc ₂ ⊕ . . . ⊕Δc _(m)

at its output.

Since the used BCH code is shortened, it can happen that a multi-biterror is mapped to the syndrome S(1) of a 1-bit error, wherein S(1) isequal to a column of the check matrix of the unshortened BCH code, whichhad been deleted when reducing the matrix. This situation can bedetected easily when the signals u_(korr) ^(OR) and c_(korr) ^(OR) areboth equal 0, but the error syndrome S(1) of a 1-bit error exists.

The proposed concept is now to be described at a particularly simpleexample of a unshortened Hamming code having four information bits u₁,u₂, u₃, u₄, four check bits c₁, . . . , c₄ and two address bits a₁, a₂.The word width k=4, m=4 and l=2 are selected to be small intentionallyin order to be able to illustrate the concept as clearly as possible.

The check matrix of the unshortened Hamming code is

$H = {\left( {1_{bin},2_{bin},3_{bin},4_{bin},\ldots \mspace{14mu},\lbrack 15\rbrack_{bin}} \right) = {\begin{pmatrix}1 & 0 & 1 & 0 & \ldots & 1 \\0 & 1 & 1 & 0 & \ldots & 1 \\0 & 0 & 0 & 1 & \ldots & 1 \\0 & 0 & 0 & 0 & \ldots & 1\end{pmatrix}.}}$

The set Sp⁰⁰ of the columns of the check matrix whose first twocomponents are equal to 0,0 is

Sp ⁰⁰={(0010)^(T),(0001)^(T),(0011)^(T)}.

The set Sp⁰¹ of the columns of the check matrix whose first twocomponents are equal to 0,1 is

Sp ⁰¹={(0110)^(T),(0101)^(T),(0111)^(T),(0100)^(T)},

The set Sp¹⁰ of the columns of the check matrix whose first twocomponents are equal to 1,0 is

Sp ¹⁰={(1010)^(T),(1001)^(T),(1011)^(T),(1000)^(T)}.

The set Sp¹¹ of the columns of the check matrix whose first twocomponents are equal to 1,1 is

Sp ¹¹={(1110)^(T),(1101)^(T),(1111)^(T),(1100)^(T)}.

As columns of the (second) sub-matrix H^(a), two linearly independentcolumns are selected from Sp⁰⁰, e.g. columns (0010)^(T), (0001)^(T).

As columns of the (third) sub-matrix H^(c), four columns are selectedfrom Sp¹⁰ and Sp⁰¹ namely columns (0100)^(T), (0111)^(T), (1000)^(T),(1001)^(T), that are linearly independent. As columns of the (first)sub-matrix H^(u), four columns are selected from Sp¹¹, namely columns(1100)^(T), (1101)^(T), (1110)^(T), (1111)^(T). In the first twocomponents, each of the values 10, 01, 11 occurs an even number oftimes, so that the XOR-sum of the first and second components of thematrix

$H = {\left( {H^{u},H^{a},H^{c}} \right) = \begin{pmatrix}1 & 1 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 \\0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1\end{pmatrix}}$

is equal 00. For the syndrome S=S₁, S₂, S₃, S₄, we have

S=H·(u,a,c)^(T)

S ₁ =u ₁ +u ₂ +u ₃ +u ₄ +c ₁ +c ₄

S ₂ =u ₁ +u ₂ +u ₃ +u ₄ +c ₂ +c ₃

S ₃ =u ₂ +u ₄ +a ₁ +c ₃

S ₄ =u ₃ +u ₄ +a ₂ +c ₃ +c ₄

For the two-dimensional binary vector a″₁, a″₂, determined according toequation (7), the following results

$s_{{All} - 1} = {{\left( {H^{u},H^{c}} \right) \cdot \left( \underset{\underset{s}{}}{{1\mspace{14mu} \ldots}\mspace{14mu},1} \right)^{T}} = (0010)^{T}}$

and, hence,

$(0010)^{T} = {\begin{pmatrix}0 & 0 \\0 & 0 \\1 & 0 \\0 & 1\end{pmatrix} \cdot \left( {a_{1}^{''},a_{2}^{''}} \right)^{T}}$

with the solution a″₁=1 and a″₂=0.

Since a″₂=0, constantly a₂=1 is set, which results in equations

S ₁ =u ₁ +u ₂ +u ₃ +u ₄ +c ₁ +c ₄

S ₂ =u ₁ +u ₂ +u ₃ +u ₄ +c ₂ +c ₃

S ₃ =u ₂ +u ₄ +a ₁ +c ₃

S ₄ =u ₃ +u ₄+1+c ₃ +c ₄

which logically describes a syndrome generator according to thedescribed concept, whose implementation may be realized, for example,with a commercially available synthesis tool.

The available addresses are here only addresses a₁, a₂=0,1 and a₁,a₂=1,1. The syndrome of the vector (0000a₁, a₂ 0000) is S=(00a₁1) and,hence, unequal 0. The syndrome of the vector (1111a₁, a₂1111) is equalS=(00ā₁1) and, hence, unequal 0. Hence, the vectors (0000a₁, a₂0000) and(1111a₁, a₂1111) are never code vectors.

Vector 0000a₁, a₂ 0100 will be considered as an example of a vectorhaving a one in the bits stored in the memory. The associated syndromeis S=(01a₁1). The same has at least 2 ones. By checking all possible1-bit errors, it is easy to confirm that no 1-bit error can modify thevector 0000a₁, a₂0100 into a code word with the error syndrome S=0.

A respective statement applies for all vectors having exactly one 1 inbits u₁, u₂, u₃, u₄ c₁, c₂, c₃,c₄. An example for the circuit fordetermining the correction values K₁ ^(u), K₂ ^(u), K₃ ^(u), K₄ ^(u), K₁^(a), K₁ ^(c), K₂ ^(c), K₃ ^(c), K₄ ^(c) is shown in FIGS. 14 a-14 i.The value S=(S₁, S₂, S₃, S₄) is inserted into the correction circuits K₁^(u) 81, K₂ ^(u) 82, K₃ ^(u) 83, K₄ ^(u) 84, K₁ ^(a) 85, K₁ ^(c) 86, K₂^(c) 87, K₃ ^(c) 88, K₄ ^(c) 89.

The correction circuit K₁ ^(u) 81 outputs the correction values Δu₁=1exactly when S=1100.

The correction circuit K₂ ^(u) 82 outputs the correction values Δu₂=1exactly when S=1110.

The correction circuit K₃ ^(u) 83 outputs the correction values Δu₃=1exactly when S=1101.

The correction circuit K₄ ^(u) 84 outputs the correction values Δu₄=1exactly when S=1111.

The correction circuit K₁ ^(a) 85 outputs the correction values Δa₁=1exactly when S=0010.

The correction circuit K₁ ^(c) 86 outputs the correction values Δc₁=1exactly when S=1000.

The correction circuit K₂ ^(c) 87 outputs the correction values Δc₂=1exactly when S=0100.

The correction circuit K₃ ^(c) 88 outputs the correction values Δc₃=1exactly when S=0111.

The correction circuit K₄ ^(c) 89 outputs the correction values Δc₄=1exactly when S=1001.

The illustrated concept is also applicable when bits u=u₁, . . . , u_(k)consist of K payload data and q bits derived therefrom. Then with k=K+q,the following applies

u ₁ , . . . ,u _(k) ,=u ₁ , . . . ,u _(K) ,w ₁ , . . . ,w _(q).

Bits w₁, . . . , w_(q) can also be referred to as inner check bits andthese bits as check bits of an inner code that are determined from bitsu₁, . . . , u_(K) by

w₁ = f₁(u₁, …  , u_(K)), w₂ = f₂(u₁, …  , u_(K)), ⋮w_(q) = f_(q)(u₁, …  , u_(K))

Thereby, f₁, . . . , f_(q) are K-digit boolean functions and k=K+qapplies. If the boolean functions f₁, . . . , f_(q) are linear, then theinner code is linear. If at least one of these functions is non-linear,then the code is non-linear.

Bits u₁, . . . , u_(k)=u₁, . . . , u_(K), w₁, . . . , w_(q) arecorrected, for example, by a shortened BCH code correcting a 2-bit errorby using its check bits c₁, . . . , c_(m). For obtaining a particularlyhigh probability for error detection of errors in bits u_(l), . . . ,u_(k) after the possible error correction by the BCH code, errordetection in bits u_(l), . . . , u_(k) can be performed by using thecheck bits of the inner code, without having to increase the number ofcheck bits of the external code.

As an example, a non-linear code described in document DE 10 2006 005836 or “Gössel, M., Otcheretny, V., Sogomonyan, E. and Marienfeld, D.:New Methods of Concurrent Checking, Springer Verlag 2008, p. 49-53” maybe used, where, here, two internal check bits are determined by

w ₁ =u ₁ u ₂ ⊕u ₃ u ₄ ⊕ . . . ⊕u _(K−1) u _(K)

and

w ₂ =u ₂

u ₃ ⊕u ₄

u ₅ ⊕ . . . ⊕u _(K)

u ₁

Any arbitrary error that does not corrupt simultaneously all bits u₁, .. . , u_(k) can then be detected advantageously at least with theprobability ½ as, for example, described in “Gössel, M., Otcheretny, V.,Sogomonyan, E. and Marienfeld, D..: New Methods of Concurrent Checking,Springer Verlag 2008, p. 49-53”. It is also possible to include theaddress bits into the determination of the check bits of the inner code.For example, w₁ and w₂ can be determined as

w ₁ =u ₁ u ₂ ⊕u ₃ u ₄ ⊕ . . . ⊕u _(K−1) u _(K) ⊕a ₁ a ₂ ⊕ . . . ⊕a_(l−1) a ₁

and

w ₂=(u ₂

u ₃ ⊕u ₄

u ₅ ⊕ . . . ⊕u _(K)

a ₁ ⊕a ₂

a ₃ ⊕ . . . ⊕a _(l)

u ₁)

It is also possible that bits w₁, . . . , w_(q) only depend on addressbits a₁, . . . , a_(l) and not on bits u₁, . . . , u_(k). For example,bits w₁, w₂ can be determined by

w ₁ ,w ₂=(a ₁+2a ₂+ . . . +2^(i−1) a ₁) mod 3

By using the proposed concept, an error correction circuit for 1-bit and2-bit errors in which the address bits are integrated into errordetection, wherein also the errors All-0 and All-1 may be detected asbeing errors in any address values, may be enabled.

Further, the described concept may enable to write, under any addressany data, in particular also the value (0, . . . , 0), (1, . . . , 1)into all data bits without all memory cells being occupied by 0 (1), sothat All-1 (All-0) is under no address a valid codeword in all memorycells.

Likewise, the circuitry may enable to differentiate every 1-bit-errorfrom errors “All-1” and “All-0”, which is advantageous. Thus, it may notbe the case that a word read out of storage in case of a correctable1-bit error is mixed up with an error “All-0” or in “All-1”.

In the following, the very detailed example described before isexplained in more general words also indicating some of the optional oradditional features.)

There is a circuitry for generating a m-digit syndrome S=(S₁, . . . ,S_(m)) of a code C correcting at least a 1-bit error of a code word ofthe length n having a check matrix H for correcting errors of bitsstored in an addressable memory. A first group u=u₁, . . . , u_(k) of kbits, a second group a=a₁, . . . , a_(l) of l bits and a third groupc=c₁, . . . , c_(m) of m bits exist, and the first group of k bits andthe third group of m bits are stored in addressable memory under theaddress a. In the error-free case, bits c=c₁, . . . , c_(m) are derivedlogically from bits u=u₁, . . . , u_(k) and a=a₁, . . . , a_(l) by XORconnections, n=k+l+m, wherein the circuitry has n inputs, where the bitsu₁, . . . , u_(k), a₁, . . . ,a_(l), c₁, . . . , c_(m) are applied,wherein bits u₁, . . . , u_(k), c₁, . . . , c_(m) are output from thememory when applying the address a₁, . . . , a_(l) and the values of theerror syndrome S=S₁, . . . , S_(m) are determined by

S=H·(u,a,c)^(T)

and (u,a,c)^(T) is the transposed column vector of the row vector(u,a,c) and the check matrix H.

The check matrix H consists of three sub-matrices H^(u), H^(a), H^(c),wherein the sub-matrix H^(u) consists of k first columns of H, thesub-matrix H^(a) consists of l second columns of H and the sub-matrixH_(c) consists of the residual m columns of H, so that

H=(H ^(u) ,H ^(a) ,H ^(c))

applies.

Further, there is a first predefined component and a second predefinedcomponent of columns of H^(u) and H^(c) each unequal [0,0] and such thatthe XOR-sum of these first predefined components of the columns of H^(u)and the columns of H^(c) component-by-component and the XOR-sum of thesecond predefined components of the columns of H^(u) and H^(c)component-by-component are each equal to 0.

The values of the first predefined component and the values of thesecond predefined component of columns of H^(a) are each equal to [0,0].

The l columns of matrix H^(a) are linearly independent.

The m columns of matrix H^(c) are linearly independent.

Further, there is a bit position r,1≦r≦l so that

${H \cdot \left( {\underset{\underset{k}{}}{1\;,\ldots \mspace{14mu},1},\underset{\underset{l}{}}{0,{\ldots \mspace{14mu} 0}},\underset{\underset{m}{}}{1,\ldots \mspace{14mu},1}} \right)} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{r - 1}^{''},0,a_{r + 1}^{''},\ldots \mspace{14mu},a_{l}^{''}} \right)^{T}}$

applies, wherein

a″ ₁ , . . . ,a″ _(r−1) ,a″ _(r+1) , . . . ,a″ _(l)ε{0, 1}

with m+l+k≦2^(m)−1 and l≦m−2.

According to an aspect, k correction circuits K₁ ^(u), . . . , K_(k)^(u) having each m inputs and an output for generating correction valuesΔu₁, . . . , Δu_(k) for XOR connection with bits u′₁, . . . , u′_(k)read out from the memory are simultaneously connected to m outputs ofthe circuit mentioned before outputting the m components of the errorsyndrome S=S₁, . . . , S_(m).

Further, the correction circuits K₁ ^(u), . . . , K_(k) ^(u) when C is a1-bit error correcting code, in the case of a 1-bit error or no errorfor j=1, . . . , k realize a m-digit boolean function K_(j) ^(u)(S) with

${\Delta \; u_{j}} = {{K_{j}^{u}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{u}} \\0 & {else}\end{matrix} \right.}$

wherein h_(j) ^(u) is the j^(th) column of the sub-matrix H^(u).

Alternatively or additionally, the correction circuits K₁ ^(u), . . . ,K_(k) ^(u), when C is a 1-bit error and 2-bit error correcting code, inthe case of a 1-bit error or a 2-bit error or no error for j=1, . . . ,k realize a m-digit boolean function K_(j) ^(u)(S) with

${\Delta \; u_{j}} = {{K_{j}^{u}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{u}} \\1 & {{{for}\mspace{14mu} S} = {h_{j}^{u\;} + h}} \\0 & {else}\end{matrix} \right.}$

wherein h_(j) ^(u) is the j^(th) column of H^(u) and h is an arbitrarycolumn of H^(u) or H^(c).

According to another aspect, the circuitry is configured such that thelogical r^(th) address bit a_(r) is set to 1 when a₁, a₂, . . . ,a_(r−1), . . . , a_(l)=0, . . . , 0 and when

a ₁ ,a ₂ . . . ,a _(r−1) ,a _(r+1) , . . . ,a _(l) =a″ ₁ ,a″ ₂ . . . ,a″_(r−1) ,a″ _(r+1) , . . . ,a″ _(l)

wherein

a″ ₁ ,a″ ₂ . . . ,a″ _(r−1) ,a″ _(r+1) , . . . ,a″ _(l)

is determined such that

${H \cdot \left( {\underset{\underset{k}{}}{1\;,\ldots \mspace{14mu},1},\underset{\underset{l}{}}{0,{\ldots \mspace{14mu} 0}},\underset{\underset{m}{}}{1,\ldots \mspace{14mu},1}} \right)} = {H^{a} \cdot \left( {a_{1}^{''},\ldots \mspace{14mu},a_{r - 1}^{''},0,a_{r + 1}^{''},\ldots \mspace{14mu},a_{l}^{''}} \right)}$

applies.

Further, it may be configured such that a_(r) is constantly set to 1.

According to a further aspect, a further sub-circuit F_(o) having k+minputs and an output for detecting the allocation All-0 of a memorycells exists, realizing an (k+m)-digit boolean function F₀(u,c), forwhich the following applies:

F ₀(u,c)=

According to an aspect, a further sub-circuit F₁ having k+m inputs andan output for detecting the allocation All-1 of a memory cells exists,realizing an (k+m)-digit boolean function F₁(u,c), for which thefollowing applies:

F ₁(u,c)=u ₁

u ₂

. . .

u _(k)

c ₁

. . .

c _(m).

Further, the check matrix H may be supplemented by a row

$\underset{\underset{k + m}{}}{1,1,\ldots \mspace{14mu},1}.$

According to another aspect, there are q components i₁, i₂, . . . ,i_(q) of the columns of the check matrix H, so that for every column hof the check matrix H, the XOR-sum of the values of these components iseach equal 1.

Additionally, a circuit component having q inputs and an output forforming the XOR-sum of the q components s_(i1), . . . , s_(iq) of theerror syndrome for forming the parity P,

P=s _(i1) ⊕ . . . ⊕s _(iq)

may exist.

According to an aspect, a further sub-circuit for address errordetection (same-bit-value-detection) may exist, which outputs an errorsignal at its output in the case of an address error.

Further, the sub-circuit for address error detection in the case thatthe code C is a 1-bit error detecting code may output, in the case of a1-bit error or no error, the value E^(a)(S) with

${E_{a}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h^{a}} \\0 & {else}\end{matrix} \right.$

wherein h^(a) is an arbitrary column of sub-matrix H^(a).

Additionally, the sub-circuit for address error detection in the casethat the code C is a 1-bit error and 2-bit error correcting code mayoutput, in the case of a 1-bit error, a 2-bit error or no error, thevalue E_(a)(S) with

${E_{a}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h^{a}} \\1 & {{{for}\mspace{14mu} S} = {h^{a\;} + h}} \\0 & {else}\end{matrix} \right.$

wherein h^(a) is an arbitrary column of matrix H^(a), h an arbitrarycolumn of matrices H_(u), H^(a), H^(c) with h≠h^(a).

According to another aspect, l additional correction circuits K₁ ^(a), .. . , K_(l) ^(a) having m inputs and one output exist, so that for j=1,. . . , l the correction circuit K_(j) ^(a) for the case that C is a1-bit error correcting code realizes a l-digit boolean function K_(j)^(a)(s), for which

${K_{j}^{a}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{a}} \\0 & {else}\end{matrix} \right.$

applies, wherein h_(a) ^(j) is the j^(th) column of check matrix H^(a).

According to a further aspect, l additional correction circuits K₁ ^(a),. . . , K_(l) ^(a) having m inputs and one output exists, so that forj=1, . . . , l the correction circuit K_(j) ^(a) for the case that C isa 1-bit error and 2-bit error correcting code realizes a l-digit booleanfunction K_(j) ^(a)(S), for which

${K_{j}^{a}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{a}} \\1 & {{{for}\mspace{14mu} S} = {h_{j}^{a\;} + h}} \\0 & {else}\end{matrix} \right.$

applies, wherein h_(j) ^(a) is the j^(th) column of check matrix ofH^(a) and h an arbitrary column of matrices H^(u) and H^(c) withh′≠h_(j) ^(a).

Additionally, the I outputs of correction circuits K₁ ^(a), . . . ,K_(l) ^(a) may be connected to inputs of a circuit having l inputs andone output, realizing the logical OR-connection of its inputs.

According to an aspect, m additional correction circuits K₁ ^(c), . . ., K_(m) ^(c) having m inputs and one output exist, wherein in the casethat C is a 1-bit error correcting code for j=1, . . . , m, thecorrection circuit K_(j) ^(c) realizes a m-digit boolean function K_(j)^(c)(S), for which, in the case for 1-bit error or no error, thefollowing applies

${\Delta \; c_{j}} = {{K_{j}^{c}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{c}} \\0 & {else}\end{matrix} \right.}$

and h_(j) ^(c) is the j^(th) column of sub-matrix H^(c).

According to another aspect m additional correction circuits K₁ ^(c), .. . , K_(m) ^(c) having m inputs and one output exist, wherein, in thecase that C is a 1-bit and a 2-bit error correcting code, for j=1, . . .,m the correction circuit K_(j) ^(c) realizes a m-digit boolean functionK_(j) ^(c)(S), for which the following applies in the case of a 1-biterror, a 2-bit error or no error:

${\Delta \; c_{j}} = {{K_{j}^{c}(S)} = \left\{ \begin{matrix}1 & {{{for}\mspace{14mu} S} = h_{j}^{c}} \\1 & {{{for}\mspace{14mu} S} = {h_{j}^{c\;} + h}} \\0 & {else}\end{matrix} \right.}$

wherein h_(j) ^(c) is the j^(th) column of sub-matrix H^(c) and h anarbitrary column of sub-matrices H^(u) or H^(c) with h≠h_(j) ^(c).

According to a further aspect, the k outputs of the correction circuitsK₁ ^(u), . . . , K_(k) ^(u) are connected into the inputs of a circuithaving k inputs and one output, realizing a logic OR connection of itsinputs.

According to an alternative aspect, the m outputs of correction circuitsK₁ ^(u), . . . , K_(k) ^(u) are connected to the inputs of a circuithaving k inputs and an output realizing a logical XOR connection of itsinputs.

Further, the m outputs of the correction circuits K₁ ^(c), . . . , K_(m)^(c) may be connected to the inputs of a circuit having m inputs and oneoutput realizing a logic OR-connection of its inputs.

Additionally, the m outputs of correction circuits K₁ ^(c), . . . ,K_(m) ^(c) may be connected to the inputs of a circuit having m inputsand one output realizing a logic XOR-connection of its inputs.

According to an aspect, the bits u_(k), . . . , u_(k−v) stored in thememory are determined from the bits u₁, . . . , u_(k−v−1) stored in thememory and the address bits a₁, . . . , a_(l) by v+1 circuits f_(k),f_(k−1), . . . , f_(k−v) each having k−v−1+l inputs and one output,realizing the (k−v+l)-digit boolean functions

u_(k) = f_(k)(u₁, …  , u_(k − v − 1), a₁, …  , a_(l)), ⋮u_(k − v) = f_(k − v)(u₁, …  , u_(k − v − 1), a₁, …  , a_(l))

Additionally, the boolean functions f_(k), . . . , f_(k−v) may notdepend on address bits a₁, . . . , a_(l).

Further, the boolean functions f_(k), . . . , f_(k−v) may not depend onbits u₁, . . . u_(k−v−1).

Additionally, at least one of the boolean functions f_(k), . . . ,f_(k−v) may be non-linear. Further, v may be equal to 1.

Additionally, f_(k) may be defined by:

f _(k)(u ₁ , . . . , u _(k−2) , a ₁ , . . . a _(i))=(u ₁

u ₂ ⊕u ₃

u ₄ ⊕ . . . ⊕u _(k−3)

u _(k−2) ⊕a ₁

a ₂ . . . ⊕a _(l−1)

a _(l))

and optionally f_(k−1) may be defined by:

f _(k−1)(u ₁ , . . . , u _(k−2) , a ₁ , . . . , a _(l))=(u ₂

u ₅ ⊕u ₄

u ₅ ⊕ . . . ⊕u _(k−4)

u _(k−3) ⊕u _(k−2)

a ₁ ⊕a ₂

a ₃ . . . ⊕a ₁

u ₁)

According to an aspect, the check matrix H_(unverk) of the not shortenedBCH code has the form

$H_{unverk} = \begin{pmatrix}\alpha^{2^{M} - 2} & \ldots & \alpha^{i} & \ldots & \alpha^{1} & \alpha^{0} \\\alpha^{3{({2^{M} - 2})}} & \ldots & \alpha^{3i} & \ldots & \alpha^{31} & \alpha^{0}\end{pmatrix}$

and the respective exponent j of a^(j) is to be interpreted modulo2^(M)−1.

According to another aspect, the correction circuit K_(i) ^(u) are atleast partly jointly implemented, the correction circuits K_(j) ^(c) andK_(i) ^(u) are at least partly jointly implemented and/or the correctioncircuits K_(i) ^(c), K_(i) ^(u) and K_(j) ^(a) are at least partlyjointly implemented.

Some embodiments according to the invention relate to an apparatus forcorrecting at least one bit error within a coded bit sequence comprisinga means for determining an error syndrome and a means for correcting biterrors. The means for determining an error syndrome may determine anerror syndrome of a coded bit sequence derived by a multiplication of acheck matrix with the coded bit sequence. The check matrix comprises afirst sub-matrix, a second sub-matrix and a third sub-matrix, eachsub-matrix comprising a plurality of lines, each line comprising aplurality of binary components. At least a first predefined component ora second predefined component of each line of the first sub-matrixcomprises a first bit value. Further, the second sub-matrix compriseslines being linearly independent from each other. The first predefinedcomponent and the second predefined component of each line of the secondsub-matrix comprises a same second bit value. The third sub-matrixcomprises lines being linearly independent from each other and the firstpredefined component or the second predefined component of each line ofthe third sub-matrix comprises the first bit-value. Further, either anXOR-sum of the first predefined components of all lines of the firstsub-matrix and the third sub-matrix is equal to the bit value 0 and anXOR-sum of the second predefined components of all lines of the firstsub-matrix and the third sub-matrix is equal to the bit value 0.Additionally, a result of a multiplication of the check matrix and thetest vector is equal to a result of a multiplication of the secondsub-matrix and a resulting vector, wherein at least one component of theresulting vector comprises the second bit value. The means forcorrecting bit errors may correct a bit error within the coded bitsequence based on the determined error syndrome of the coded bitsequence.

Some further embodiments according to the invention may relate to adecoder 1500 for decoding a faulty, coded bit sequence as it is shown inFIG. 15. The decoder 1500 may comprise an apparatus for correcting a biterror within a coded bit sequence according to the concept describedabove and a decoding unit 1510. The decoding unit 1510 may decode thecorrected bit sequence 122 provided by the apparatus for correcting abit error within a coded bit sequence to obtain a decoded bit sequence1512.

FIG. 16 shows a flow chart of a method 1600 for correcting at least onebit error within a coded bit sequence according to an embodiment of theinvention. The method 1600 comprises determining 1610 an error syndromeof a coded bit sequence derivable by a multiplication of a check matrixwith the coded bit sequence. The check matrix comprises a firstsub-matrix, a second sub-matrix and a third sub-matrix, each sub-matrixcomprising a plurality of lines, each line comprising a plurality ofbinary components. Further, at least a first predefined component or asecond predefined component of each line of the first sub-matrixcomprises a first bit value. The second sub-matrix comprises lines beinglinearly independent from each other and the first predefined componentand the second predefined component of each line of the secondsub-matrix comprises a second bit value. The third sub-matrix compriseslines being linearly independent from each other and the firstpredefined component or the second predefined component of each line ofthe third sub-matrix comprises the first bit value.

Further, an XOR-sum of the first predefined components of all lines ofthe first sub-matrix and the third sub-matrix is equal to the second bitvalue and an XOR-sum of the second predefined components of all lines ofthe first sub-matrix and the third sub-matrix is equal to 0.Additionally, the result of a multiplication of the check matrix and atest vector is equal to a result of a multiplication of the secondsub-matrix and a resulting vector, wherein at least one component of theresulting vector comprises the second bit value. Further, the method1600 comprises correcting 1620 a bit error within the coded bit sequencebased on the determined error syndrome of the coded bit sequence.

Additionally, the method 1600 may comprise further steps representingone or more of the optional aspects of the proposed concept describedabove.

FIG. 17 schematically illustrates the elements of the Galois fieldGF(2^(M)) and different subsets of elements of the Galois fieldGF(2^(M)) in a Venn diagram form or set theory diagram form. Asexplained further above, it is possible to divide the Galois field infour disjoint sets Sp⁰⁰, Sp⁰¹, Sp¹⁰, and Sp¹¹. The elements of eachdisjoint set, e.g. Sp⁰⁰, are characterized in that they have the samefirst (selected) components (j-th component) with the value “0” andsecond (selected) components (k-th component) with the value “0” (and inan analogue manner for the three other disjoint sets Sp⁰¹, Sp¹⁰, Sp¹¹).The components of the various disjoints sets in GF(2^(M)) can be usedfor different ones of the sub-matrices H^(u), H^(a), and H^(c) ascolumns or rows. For example, some of the elements of the set Sp⁰⁰ maybe used for the submatrix H^(a) as columns and thus form an errordetecting code for the address bits. The three remaining sets Sp⁰¹,Sp¹⁰, Sp¹¹ may be used together (dashed curve) and some of theirelements may be used as columns in the sub-matrices H^(u) and H^(c) inorder to thereby form an H-matrix of an error correcting code for theinformation bits u and the check bits c, for example an error correctingcode for correcting up to t-bit errors within the information bits(payload data bits) u and the check bits c.

FIG. 17 also illustrates graphically how each of the four disjoint setsSp⁰⁰, Sp⁰¹, Sp¹⁰, and Sp¹¹ can be further subdivided. In particular, thesets Spe¹⁰, Spe⁰¹, Spe¹¹ are formed from the sets Sp¹⁰, Sp⁰¹ and Sp¹¹ bydeleting two random columns each and summarizing the deleted column intothe sets Sp2¹⁰, Sp2⁰¹ and Sp2¹¹, respectively. Thus, the set Sp2⁰¹contains the two columns which were deleted from the set Sp⁰¹ in orderto determine the set Spe⁰¹. The union of the sets Spe¹⁰, Spe⁰¹, Spe¹¹,i.e., {Spe¹⁰∪Spe⁰¹∪Spe¹¹}, may be used to select m linearly independentcolumns from, designated by h₁ ^(c), . . . h_(m) ^(c) and which form thematrix (third sub-matrix)

H ^(c)=(h ₁ ^(c) , . . . ,h _(m) ^(c))

From the set Spe⁰⁰ l columns are determined which are linearlyindependent. These columns are designated by h_(l) ^(a), . . . , h_(l)^(a) and they form the matrix (second sub-matrix).

H ^(a)=(h ₁ ^(a) , . . . ,h ₁ ^(a)).

The matrix H^(u) (first sub-matrix) consists of k columns h₁ ^(u), . . ., h_(k) ^(u), wherein

h _(i) ^(u) ε{Spe ¹⁰ ∪Spe ⁰¹ ∪Spe ¹¹ }\SP ^(H) ^(c)

apply and wherein at least one column from Spe¹⁰, at least one columnfrom Spe⁰¹ and at least one column from Spe¹¹ is contained in (h₁ ^(u),. . . , h_(k) ^(u)).

Subdividing the Galois field GF(2^(M)) as schematically shown in FIG. 17(or in a similar manner) makes it possible to select the columns (ormore generally, elements) of the sub-matrices H^(u), H^(a), and H^(c) insuch a manner so that, in case a correctable error occurs in theinformation bits u or the check bits c, or a detectable error occurs inthe address bits (or more generally, identifier bits) a, thecorresponding error syndromes are clearly distinguishable and differentfor the various error classes. In other words, a detectable error in theaddress bits (identifier bits) a does typically not lead to an errorsyndrome that is associated with a correctable error in the informationbits u or check bits c, due to the aforementioned properties andselection of the elements of the sub-matrices.

The following part of the specification describes two special cases ofthe proposed error correction and detection in more detail. FIGS. 18 to27 and the accompanying description relate to an error correcting codewith 1-bit correction and address error detection. FIGS. 28 to 37 relateto an error correcting code with two-bit correction or more-bitcorrection and address error detection. The term “two-bit correction”typically means that a single erroneous bit or two erroneous bits can becorrected. In an analogue manner, the term “multi-bit correction”typically means that all errors from a single erroneous bit to a maximalcorrectable number of t erroneous bits can be corrected.

The suggestions described below in connection with FIGS. 18-27 may aim,for example, at facilitating the design of an error correction code(ECC) with a very high probability of address error detection (or moregenerally: identification data error detection), of All-0 detection andAll-1 detection for an ECC with 1-bit error correction, 2-bit errordetection with the same number of check bits which are typically neededby an ordinary Hsiao Code.

The data bits may be stored unmodified in the memory.

Without address error detection, the following may happen: If an addresserror occurs, data are read from an erroneous address location and thesedata may be completely different from the requested data. Therefore itis desirable to detect address errors with high probability. If anaddress error is mapped to an error syndrome of a correctable error orto the error syndrome 0, the address error might not be detected andconsequently result in a miscorrection or in no correction.

Furthermore, it may also be desired that All-0 and All-1 situations canbe detected for an arbitrary address. Accordingly, the problems thatmight be solved are:

-   -   to achieve a high probability for address error detection    -   simultaneously to guarantee All-0 and All-1 detection for        arbitrary addresses with 100%    -   to use no more check bits than for an ordinary Hsiao Code.

As alternatives to the solution(s) proposed herein, in particular withrespect to FIGS. 18-27, additional ROMs may be used for regeneration ofthe addresses from active word lines and bit lines and to compare theregenerated addresses with the applied addresses. However, theseadditional ROMs are typically relatively costly.

As another alternative, in case of 2-bit ECC, additional check bits mayhave to be added, to guarantee the necessary high error detectionprobability for the arbitrary address errors since a relatively largenumber of arbitrary errors might be mapped to 1-bit and 2-bit errorsyndromes or in general to t-bit error syndroms. The costs are typicallya large wordlength of the memory.

According to the suggestions that will be described in more detail inconnection with FIGS. 18-27, the H-matrix of the code is designed suchthat an arbitrary address fault is never mapped to a syndrome of acorrectable error of the data bits or check bits. This property isindependent of the used address.

Only the few address errors mapped to the syndrome 0 are not detected.An address error detection of 99.2% for 256 data bits and of 96.875% for64 bits can be achieved without enlarging the number of check bits forthe ordinary Hsiao Code.

Addresses may be mapped to fewer compacted address bits. It is possibleto map arbitrary addresses to compacted address bits which are always ≠0for arbitrary addresses. The number of compacted address bits may beequal to the number of check bits minus 2 of the code. Address errorsare also mapped to errors in the compacted address bits. The submatrixof the H-matrix corresponding to the compacted address bits may bedenoted by H^(A). The columns of the sub-matrix H^(A) of the H-matrixcorresponding to the compacted address bits are linearly independent.

According to some examples for implementation, the first two rows of thesub-matrix H^(a) (or of the matrix H^(A)) are both All-1 rows. TheXOR-sum of the columns of the H-matrix corresponding to the data andcheck bits is 0. It can be shown that All-1 or All-0 is mapped to anon-correctable error of the code for an arbitrary address.

The columns of the sub-matrix H^(c) corresponding to the check bits maybe an identity matrix and the H-matrix is in the systematic form.Therefore, data bits can be directly written into the memory and readalso unchanged from the memory. The proposed solution is typicallyrelatively cost effective with no additional check bits or ROMs needed.

The decoder is designed such that no address error is mapped to asyndrome of a correctable error. The decoder may be further designedsuch that All-1 and All-0 has a syndrome of a non-detectable error foran arbitrary address. The addresses may be compacted for fewer compactedaddress bits which are always ≠0. An address error may be mapped to anerror of the compacted address bits.

FIG. 18 schematically shows a circuitry comprising an addressable memorywith a syndrome generator arrangement connected to the addressablememory. An error syndrome S=S₁, . . . , S_(m) is produced by thesyndrome generator arrangement.

A code word of an error correcting code C is stored in a memory Spei 12.The memory Spei 12 has k+m binary data inputs, via which m check bitsc₁, . . . , c_(m) and k data bits u₁, . . . , u_(k) are provided asinput to the memory Spei, which are stored under (or at) the writeaddress a₁, . . . , a_(l). The write address a₁, . . . , a_(l) isapplied to the l bit wide address line of the memory. The check bits c₁,. . . , c_(m) are determined on the basis of the k data bits u₁, . . . ,u_(k) and the address bits a₁, . . . , a_(l) of the write address in aunambiguous manner, as will be described below.

When reading the possibly erroneous check bits c′₁, . . . , c′_(m) andthe possibly erroneous data bits u′₁, . . . , u′_(k) from the memorySpei 12 under a read address a′₁, . . . , a′₁, the possibly erroneouscheck bits c′₁, . . . , c′_(m) and the possibly erroneous data bits u′₁,. . . , u′_(k) are presented at the m+k binary inputs of a syndromegenerator arrangements Syndb 31. The syndrome generator arrangementsSyndb 31 comprises further l binary inputs at which the read addressa′₁, . . . , a′_(l) is provided, under which the possibly erroneouscheck bits and possibly erroneous data bits have been read out from thememory Spei 12. The syndrome generator arrangement Syndb 31 outputs, onthe basis of the inputted data bits u′₁, . . . , u′_(k), the check bitsc′₁, . . . , c′_(m) and the address bits a′₁, . . . , a′_(l) of the readaddress, a m-component error syndrome S₁, . . . , S_(m).

The syndrome generator arrangement Syndb 31 is configured such that theerror syndrome of an arbitrary error in the read address is differentfrom all syndroms of a 1-Bit error (or of 1-bit errors) in the data bitsor in the check bits. Since 1-Bit errors in the data bits and in thecheck bits are correctable using the code C, it may be desirable that anarbitrary address error that shall be detected, but shall not result ina correction of the data bits or check bits, is different in its errorsyndrome from the error syndrome of each 1-bit error in the data bitsand the check bits.

FIG. 19 schematically shows a special implementation example of asyndrome generator arrangement Syndb 31. The syndrome generatorarrangement Syndb 31 comprises a syndrome generator Synd 1931 with kinputs for inputting the possibly erroneous data bits u′₁, . . . ,u′_(k), m inputs for inputting the possibly erroneous check bits c′₁, .. . , c′_(m), and b binary inputs for the input of b compacted bits A′₁,. . . , A′_(b) derived from the address bits of the read address a′₁, .. . , a′_(l) with l>b. The syndrome generator Synd 1931 furthercomprises m binary outputs for outputting the error syndrome S₁, . . . ,S_(m) and a combinational circuit Akomp 1922 for compacting the addressbits with l inputs and b outputs, which are connected with bcorresponding inputs of the syndrome generator Synd.

When the bits of the read address a′₁, . . . , a′_(l) are presented atthe input(s) of the combinational circuit Akomp 1922 for compacting ofthe address bits, then this circuit outputs at its output the bits A₁ .. . , A′_(b) of the compacted address. The combinational circuit Akomp1922 is configured that the bits A′₁, . . . , A′_(b) are determinedaccording to the relation

A′ ₁ , . . . ,A′ _(b) =F(a′ ₁ , . . . ,a′ ₁),

wherein F is a function that maps l-tuple binary values in b-tuplebinary values, wherein special useful implementation examples of thefunction F will be described below.

The syndrome generator Synd 1931 is in this implementation exampleconfigured so that it outputs an error syndrome S₁, . . . ,S_(m), thatis determined by

S ₁ , . . . ,S _(m) =H·(c′ ₁ , . . . ,c′ _(m) ,u′ ₁ , . . . ,u′ _(k) ,A′₁ , . . . ,A′ _(b))^(T),

wherein H is a H-matrix of the code C, wherein in this implementationexample the H-Matrix is considered in its systematic form. Note that thecolumns (or generally, the elements) of H-matrix Hcould be arranged in adifferent manner so that the order of check bits c, the information bitsu, and the compacted address bits A may be changed. Accordingly, theerror syndrome S₁, . . . , S_(m) may be alternatively determined by

S ₁ , . . . ,S _(m) =H·(u′ ₁ , . . . ,u′ _(k) ,A′ ₁ , . . . ,A′ _(b) ,c′₁ , . . . ,c′ _(m))^(T),

for example.

FIG. 20 schematically shows an implementation example of the invention.The circuitry of FIG. 20 comprises the combinational circuit Akomp1 2034for compacting the write address a₁, . . . , a_(l) in compacted addressbits A₁, . . . , A_(b), the combinational circuit Akomp2 2035 forcompacting the read address a′₁, . . . , a′_(l) in compacted addressbits A′₁, . . . , A′_(b), a combinational circuit Prü 21 (similar to thecoder in systematic form 21) for forming m check bits c₁, . . . , c_(m)from the data bits u₁, . . . , u_(k) and the compacted address bits A₁,. . . , A_(b) of the write address, a memory Spei 12 with m+k datainputs for inputting the check bits c₁, . . . , c_(m) and the data bitsu₁, . . . , u_(k) with m+k data outputs for outputting the possiblyerroneous check bits c′₁, . . . , c′_(m) and the possibly erroneous databits u′₁, . . . , u′_(k) and a l bit wide address input for inputting awrite address a₁, . . . , a_(l) or read address a′₁, . . . , a′_(l), anda syndrome generator Synd 33 with k+m+b inputs for inputting thepossibly erroneous data bits u′₁, . . . , u′_(k), the possibly erroneouscheck bits c′₁, . . . , c′_(m) and the compacted address bits A′₁, . . ., A′_(b), and m binary outputs for outputting the error syndrome S=S₁, .. . , S_(m).

The address line, that carries the write address, is connected with thel-component input of the combinational circuit Akomp1 2034 and is alsofed into the address input of the memory Spei 12. The data line whichcarries the data bits u₁, . . . , u_(k) is connected to both the k firstinputs of the combinational circuit Prü 21 for forming the check bitsand also such to k first data inputs of the memory Spei 12. The b bitwide output of the combinational circuit Akomp1 2034 is fed to thefurther b binary inputs of the combinational circuit Prü 21. The m bitwide output of the circuit Prü 21 is connected with the further m datainputs of the memory Spei 12.

When the write-signal is active, the data provided at the data inputs ofthe memory are written to the memory at the provided address. Thewrite-signal is not depicted in FIG. 20.

The address line that carries the read address is connected with thel-component input of the combinational circuit Akomp2 2035 and also fedto the address input of the memory Spei 12.

The first m data outputs of the memory Spei 12 carrying the possiblyerroneous check bits C′₁, . . . , c′_(m) are connected with m firstinputs of the syndrome generator Synd 1931. The further k data outputsof the memory Spei 12 carrying the possibly erroneous data bits u′₁, . .. , u′_(k) are connected with further k inputs of the syndrome generatorSynd 1931. The output of the combinational circuit Akomp2 2035 isconnected with the further b inputs of the syndrome generator Synd 1931.When the read-signal is active, the data stored at the applied addressare output to the corresponding data outputs of the memory. Theread-signal is not depicted in FIG. 20.

The combinational circuit Akomp1 2034 is configured so that it forms thecompacted bits A₁, . . . , A_(b) according to the relation

A ₁ , . . . ,A _(b) =F(a ₁ , . . . ,a _(l))

on the basis of the write address a₁, . . . , a_(l), wherein F is acombinational function that maps l-tuple binary values to b-tuple binaryvalues.

The combinational circuit Akomp2 2035 is configured so that it forms thecompacted bits A′₁, . . . , A′_(b) according to the relation

A′ ₁ , . . . ,A′ _(b) =F(a′ ₁ , . . . ,a′ _(l))

on the basis of the read address a′₁, . . . , a′_(l), wherein F is thesame combinational function as it is implemented for the circuit Akomp12034. Useful implementation examples of the function F are describedbelow.

The syndrome generator Synd 1931 is configured so that it forms theerror syndrome S using the H-matrix of the code C according to therelation

S=H·[c′ ₁ , . . . ,c′ _(m) ,u′ ₁ , . . . ,u′ _(k) ,A′ ₁ , . . . ,A′_(b)]^(T),

wherein H has the form

H=(H ^(c) ,H ^(u) ,H ^(A)),

H^(c) is a m-dimensional identity matrix, H^(u)=(h₁ ^(u) , . . . , h_(k) ^(u)) is a (m, k)-matrix. The first two components of each columnh_(i) ^(u) are unequal [1,1]. The number of 1-s (ones) in every columnof H^(u) and H^(c) is odd. Thus H^(c) H^(u) are forming an H-matrix of a1-bit-error correction and a 2-bit-error detection Hsiao-Code. Thematrix H^(A)=h₁ ^(A), . . . , h_(b) ^(A) is a (m, b)-matrix for whichthe following holds:

$\begin{matrix}{H^{A} = {\left( {h_{1}^{A},\ldots \mspace{20mu},h_{b}^{A}} \right) = \begin{pmatrix}\underset{\underset{b}{}}{1,\ldots \mspace{14mu},1} \\\underset{\underset{b}{}}{1,\ldots \mspace{14mu},1} \\I_{b}\end{pmatrix}}} & (11)\end{matrix}$

with b=m−2 and each column of the matrix H having an odd number of ones.I_(b) is the b-dimensional identity matrix. The matrix H^(A) correspondsapproximately to the matrix H^(a) mentioned above, where instead of theaddress bits a₁, . . . , a_(l) compacted address bits A₁, . . . , A_(b)are used.

We shall now demonstrate:

if the error syndrome of an address error of the read address is unequal0, then it is different from every error syndrome of 1-Bit errors in thedata bits or in the check bits.

Assume a₁, . . . , a_(l) with A₁, . . . , A_(b)=F(a₁, . . . , a_(l)) tobe the correct read address and, in case of an address error φ, a₁ ^(f),. . . , a_(l) ^(f) with A₁ ^(f), . . . , A_(b) ^(f)=F(a₁ ^(f), . . . ,a_(l) ^(f)) the erroneous read address, then the difference ΔA₁, . . . ,ΔA_(b) of the compacted, correct read address and the compactederroneous read address is equal to

ΔA ₁ , . . . ,ΔA _(b) =A ₁ ⊕A ₁ ^(f) , . . . ,A _(b) ⊕A _(b) ^(f).

The error syndrome s_(φ) corresponding to the address error φ, ist then

$\begin{matrix}\begin{matrix}{s_{\phi} = {H^{A} \cdot \left( {{\Delta \; A_{1}},\ldots \mspace{14mu},{\Delta \; A_{b}}} \right)^{T}}} \\{= s_{\phi}} \\{= {H^{A} \cdot \left( {{\Delta \; A_{1}},\ldots \mspace{14mu},{\Delta \; A_{b}}} \right)}} \\{= {\begin{bmatrix}{\Delta \; {A_{1} \otimes \ldots \otimes \Delta}\; A_{b}} \\{\Delta \; {A_{1} \otimes \ldots \otimes \Delta}\; A_{b}} \\{\Delta \; A_{1}} \\{\Delta \; A_{2}} \\\vdots \\{\Delta \; A_{b}}\end{bmatrix}.}}\end{matrix} & (12)\end{matrix}$

We shall now consider two cases:

-   -   The number of the ones in ΔA₁, . . . , ΔA_(b) is even. According        to equation (12) we then have

$\begin{matrix}{{s_{\phi} = \begin{bmatrix}0 \\0 \\{\Delta \; A_{1}} \\{\Delta \; A_{1}} \\\vdots \\{\Delta \; A_{b}}\end{bmatrix}},} & (13)\end{matrix}$

and s_(φ) exhibits an even number of ones. However, each column of thematrices H^(c) and H^(u) has an odd number of ones. Since each 1-biterror in the data or in the check bits corresponds to an error syndromethat is equal to one column of the matrices Hr or H^(u), the errorsyndrome s_(φ) is unequal to each error syndrome of a 1-bit error in thedata bits or the check bits.

-   -   The number of the ones in ΔA₁, . . . , ΔA_(b) is odd. According        to equation (12) we then have

$\begin{matrix}{s_{\phi} = {\begin{bmatrix}1 \\1 \\{\Delta \; A_{1}} \\{\Delta \; A_{1}} \\\vdots \\{\Delta \; A_{b}}\end{bmatrix}.}} & (14)\end{matrix}$

The first two components of s_(φ) are now equal to [1,1]. Since thefirst two components of each column of the matrices H^(c) and H^(u) areunequal [1,1] in each case (i.e., for each column), the error syndromes_(φ) is different from every error syndrome of a 1-bit error in thedata bits or check bits.

It is of course possible to interchange or swap individual rows of theH-matrix H without changing the spirit of the invention. The arrangementof the rows of the H-matrix H, and consequently also in the matrix H^(A)have been chosen herein in order to facilitate a simple andcomprehensible description. It is possible to interchange or swap thefirst row with the fourth row. Consequently the second row and thefourth row of the matrix H^(A) will present all ones in this case, andthe swapped new first row is then the previous fourth row

$\underset{\underset{b}{}}{{0,1,{0\mspace{14mu} \ldots}\mspace{14mu},0}\mspace{31mu}},$

and so on.

FIG. 21 schematically shows a special implementation example of theinvention.

Circuit portions or sub circuits that are implemented in a separatemanner in the implementation example of FIG. 20, are implemented in apartially joint manner in FIG. 21.

The circuitry in FIG. 21 comprises

-   -   a combinational circuit Akomp 2142 for compacting both a write        address a₁, . . . , a_(l) in corresponding compacted address        bits A₁, . . . , A_(b), as well as a read address a′₁, . . . ,        a′_(l) in corresponding compacted bits A′₁, . . . , A′_(b),    -   a multiplexer MUX 2141 having a control input to which a binary        control signal w/r (write/read) is fed, which assumes the value        “1” when the write signal w is active, and assumes the value “0”        when the read signal r is active, and which connects its 1-input        (first multiplexer input) with its output, when the control        signal is equal 1, and connects its 0-input (second multiplexer        input) with its output, when the control signal assumes the        value “0”,    -   a check bit former Prü 21 with b+k binary inputs and m binary        outputs for determining check bits. The check bit former Prü 21        forms the check bits c₁, . . . , c_(m) on the basis of the        compacted address bits A₁, . . . , A_(b) and the data bits u₁, .        . . , u_(k) when the write signal w is active. When the read        signal r is active, the check bit former Prü 21 determines the        check bits c*₁, . . . , c*_(m) on the basis of the compacted        address bits A′₁, . . . , A′_(b) and on the basis of the data        bits u′₁, . . . , u′_(k) read out from the memory Spei 12,    -   a demultiplexer DEMUX 2144 with m binary inputs and a first and        a second output, each m bit wide, wherein the demultiplexer        DEMUX 2144 comprises a control input to which the binary control        signal w/r (write/read) is applied. When the write signal w is        active, the binary control signal w/r assumes the value 1 and        when the read signal is active, the binary control signal w/r        assumes the value 0. The demultiplexer DEMUX 2144 is configured        to connect its input with its 1-output (first demultiplexer        output), when the control signal is equal 1, and to connect its        input with its 0-output, when the control signal assumes the        value 0,    -   a memory Spei 12 with k+m data inputs for inputting the data        bits u₁, . . . , u_(k) to be written and the corresponding check        bits c₁, . . . , c_(m), with k+m data outputs for outputting the        possibly erroneous data bits u′₁, . . . , u′_(k) to be read and        the corresponding possibly erroneous check bits c′₁, . . . ,        c′_(m), and l address inputs for inputting a write address a₁, .        . . , a_(l) or a read address a′₁, . . . , a′_(l),    -   and a XOR-circuit 2146 with 2·m binary inputs and m binary        outputs for componentwise XOR-combining the check bits c′₁, . .        . , c′_(m) and C*₁, . . . , c*_(m) to an error syndrome

S ₁ , . . . ,S _(m) =c′ ₁ ⊕c* ₁ , . . . ,c′ _(m) ⊕c* _(m).

The address line which carries the write address a₁, . . . , a_(l) whenwriting or the read address a′₁, . . . , a′_(l) when reading, isconnected with the l bit wide input of the combinational circuit Akomp2142. This combinational circuit 2142 outputs at its output thecompacted bits A₁, . . . , A_(b) of the write address or the compactedbits A′₁, . . . , A′_(b) of the read address, respectively. The circuitAkomp 2142 is configured to determine the compacted bits according tothe relation

A ₁ , . . . ,A _(b) =F(a ₁ , . . . ,a _(l))

and

A′ ₁ , . . . ,A′ _(b) =F(a′ ₁ , . . . ,a′ _(l)).

In this context F is a combinational function that maps the l-tuplebinary values to b-tuple binary values, wherein b<l.

Furthermore the address line which carries upon writing the writeaddress a₁, . . . , a_(l) or upon reading the read address a′₁, . . . ,a′_(l) is connected with the l bit wide address input of the memory Spei12.

The b bit wide output of the combinational circuit Akomp 2142 isconnected with first b binary inputs of the check bit former 2143.

The m bit wide output of the check bit former 21 is connected with theor-bit wide input of the demultiplexer DEMUX 2144. The m bit wide firstoutput of the demultiplexer DEMUX 2144 is connected with m first datainputs of the memory Spei 12, further k data inputs of which areconnected with the input line that carries the data bits u₁, . . . ,u_(k) and which is in addition connected to the 1-input of themultiplexer MUX 2141.

The m bit wide 0-output of the demultiplexer DEMUX 2144 is fed to afirst m bit wide input of the XOR-circuit 2146, of which a second m bitwide input is connected with the first m data outputs of the memory Spei12, which outputs upon reading the possibly erroneous check bits c′₁, .. . , c′_(m), and which in the case of the reading operation arecombined in the XOR-circuit 2146 with the bits c*₁, . . . , c*_(m) toyield the error syndrome S₁, . . . , S_(m), which is provided at theoutput of the XOR-circuit.

When reading, the possibly erroneous data bits u′₁, . . . , u′_(k) thatare provided to the 0-input of the multiplexer MUX 2141, are output atthe second k bit wide output of the memory Spei 12. When reading, the0-input of the multiplexer 2141 is connected with its output so that thepossibly erroneous data bits u′₁, . . . , u′_(k) are provided at thesecond k bit wide input of the check bit former Prü 21. The compactedbits A′₁, . . . , A′_(b) are provided at the first b bit wide input ofthe check bit former Prü 21.

The check bit former Prü 21 is configured to form the check bits c*₁, .. . , c*_(m) according to the relation

c* ₁ , . . . ,c* _(m)=(u′ ₁ , . . . ,u′ _(k) ,A′ ₁ , . . . ,A′ _(b))·P

and provides them at its output. In this context, P designates theparity matrix of the contemplated code C.

When writing, the 1-input of the multiplexer 2141 is connected with itsoutput so that the data bits u₁, . . . , u_(k) are provided at thesecond, k bit wide input of the check bit former Prü 21. Now thecompacted bits A₁, . . . , A_(b) are provided at the first b bit wideinput of the check bit former Prü 21. The check bit former Prü 21 isconfigured so that it forms the check bits C₁, . . . , C_(m) accordingto the relation

c ₁ , . . . ,c _(m)=(u ₁ , . . . ,u _(k) ,A ₁ , . . . ,A _(b))·P

and provides them at its output.

FIG. 22 illustrates the reading of data from the memory Spei 12. Thecircuit components of FIG. 22 are designated with the same referencenumerals as in FIG. 21.

Since the multiplexer MUX 2141 in FIG. 21 connects its 0-input with itsoutput when the control signal “reading” (r) is active, the data outputof the memory Spei 12 from FIG. 21 carrying the possibly erroneous databits u′₁, . . . , u′_(k) is in FIG. 22 connected directly with thesecond k bit wide input of the check bit former Prü 21.

Since the demultiplexer DEMUX 2144 in FIG. 21 connects its input withits 0-output when the control signal “reading” (r) is active, the outputof the check bit former 21 in FIG. 22, which carries the bits c*₁, . . ., c*_(m), is connected directly with the first input of the XOR-circuit2146. The possibly erroneous check bits c′₁, . . . , c′_(m) provided bythe memory 12 are provided at the second input of the XOR-circuit 2146.

In FIG. 22 it is illustrated that the check bit former Prü 21 and theXOR-circuit 2146 form a syndrome generator Synd 2248 of the contemplatedsystematic code C and that the combinational circuit Akomp 2142, thecheck bit former Prü 21 and the XOR-circuit 2146 form a syndromegenerator arrangement Syndb 2247.

FIG. 23 illustrates the writing of data in the memory Spei 12 of thecircuitry of FIG. 21.

The circuit components of FIG. 23 are designated with the same referencenumerals as in FIG. 21.

Since the multiplexer MUX 2141 in FIG. 21 connects its 1-input with itsoutput when the control signal w is active, the data input carrying thedata bits u₁, . . . , u_(k) is connected in FIG. 23 directly with thesecond k bit wide input of the check bit former Prü 21. The compactedbits A₁, . . . , A_(b), which are output by the combinational circuitAkomp 2142, are provided at the first b inputs of the check bit formerPrü 21. The combinational circuit Akomp 2142, which upon reading is partof the syndrome generator arrangement 2247 in FIG. 22, serves for theformation of the compacted bits A₁, . . . , A_(b) on the basis of thewrite address a₁, . . . , a_(l) upon writing. FIG. 23 illustrates thatthis portion of the circuit is used commonly upon writing and uponreading in the illustrated implementation example of the invention. Thecheck bit former Prü 21 outputs the check bits c₁, . . . , C_(m) at itsm bit wide output, which are applied along with the data bits u₁, . . ., u_(k) to the data inputs of the memory 12. The check bit former 21 isalso commonly used upon writing and reading.

In case the circuitry, as it is for example illustrated in FIG. 21, isoptimized using a synthesis tool, gates of the circuit are then usuallyused jointly in different circuit portions, as it is common in circuitdesign, so that partial circuits are implemented at least in part in ajoint or common manner.

FIG. 24 schematically illustrates a syndrome generator arrangement Syndb31 of FIG. 18. An error syndrome S₁, . . . , S_(m) is output at theoutput of the syndrome generator arrangement Syndb 31 and an errordetection circuit FE 2451 is connected to the output of the syndromegenerator arrangement Syndb 31. The error detection circuit FE 2451 hasa m bit wide input and a R bit wide output wherein R≧1. In thisimplementation example the syndrome generator arrangement Syndb 31 isconfigured so that it generates different syndromes for all 1-Bit errorsin the data bits and check bits, which are also different from thesyndromes of all 2-Bit errors in the data bits and the check bits. Ifthe number of 1s in all columns of the H-matrix is odd, the consideredcode is a shortened Hsiao-Code.

Then the error detection circuit FE 2451 may be configured to output,for each syndrome of a 1-Bit-error in the data bits or check bits thatis equal to a column of the H-matrix of the contemplated code C, a firstvalue E₁, and to output a value E₀ different to the first value E₁, whenthe error syndrome is equal 0, and to output a further value E₂, whenthe syndrome is unequal 0 and assumes a value that is not equal to acolumn of the matrices H^(u) or H_(c). The value E₂ indicates anuncorrectable error when the code C is a 1-bit error correcting and2-Bit error detecting shortened Hsiao code.

Only those multi-bit errors that are mapped to a syndrome equal 0 arenot detected, and only those multi-bit errors that are mapped to asyndrome, which is equal to one of the columns of the H-matrix, whichare assigned to the data bits or the check bits, are correctederroneously. All further multi-bit errors are detected as uncorrectableerrors. In other words: When multi-bit errors are mapped to a syndromethat does not correspond to any column of the H-matrix relative to thedata bits or the check bits, these multi-bit errors are indicated asnon-correctable (uncorrectable) errors.

In the described implementation example it holds that R=2. It is alsopossible that the error detection circuit outputs a first value E₀ whenthe error syndrome is equal 0 and when the error syndrome is the errorsyndrome of a correctable error, and outputs a second value E₁ differentfrom the first value when via the error syndrome an error is indicatedthat is not correctable by the code. In this case it is possible tochoose R=1.

FIG. 25 schematically shows a special implementation example of errordetection and error correction. A syndrome generator arrangement Syndb31 of FIG. 18 provides at its output an error syndrome S₁, . . . ,S_(m), wherein this output is connected with the input of a decoder Dec2561 and simultaneously with the input of a first error detectioncircuit FE1 2562. The R′ bit wide output of the first error detectioncircuit FE1 2562 which carries the error signal E′ is connected with aR′ bit wide input of a second error detection circuit FE2 2563, a secondk+m bit wide input of which is connected to the k+m bit wide output ofthe decoder Dec 2561, and which provides at its R* bit wide output anerror signal E*. The k first output lines of the decoder Dec 2561, whichcarry the correction values e₁, . . . , e_(k) for the possibly erroneousdata bits u′₁, . . . , u′_(k), are fed to a first k bit wide input of aXOR circuit 2564. The values u′₁, . . . , u′_(k) are provided at thesecond input of the XOR circuit 2564 which has a width of k bits, too.The XOR circuit 2564 provides at its k bit wide output the correcteddata bits

u ₁ ^(cor) , . . . ,u _(k) ^(cor) =u′ ₁ ⊕e ₁ , . . . ,u′ _(k) ⊕e _(k).

In this implementation example it is assumed, that all columns of theH-matrix of the used code C present an odd number of ones and arepairwise different, wherein however not all possible columns with an oddnumber of ones and m components actually occur as columns of theH-matrix, because the code is a so called shortened Hsiao-code.

All 1-Bit errors in the data bits or the check bits can be corrected.

The error detection circuit FE1 2562 is here configured that itdetermines a first value E′₀ when the error syndrome is equal 0, that itdetermines a second, different value E′₁ when the error syndromeexhibits an odd number of ones, and that it determines a third valueE′₂, when the error syndrome is unequal to 0 and presents an even numberof ones.

In case a 1-Bit error occurs in the data bits or the check bits, thenthe error syndrome exhibits an odd number of ones, and error signaloutput by the error detection circuit FE1 is equal E′₁.

However, it is also possible that an error syndrome occurs with an oddnumber of ones in the case of a multi-bit error, for example a 3-Biterror or a 5-Bit-error. In this situation it is possible that amulti-bit error corresponds to an error syndrome with an odd number ofones, which does not appear as column of the H-matrix. By using theerror detection circuit FE2 2563 such a case can be detected.

The error detection circuit FE2 2563 is here configured that it checkswhether actually a single correction signal e₁, . . . , e_(k+m) equal 1has been produced by the decoder Dec 2561, when the first errordetection circuit FE1 2562 determines a value E′₁. In this manner it canbe excluded that a multi-bit error, that results in an error syndromewith an odd number of ones, but that is not equal to any column of theH-matrix corresponding to the data bits or the check bits, iserroneously indicated as a correctable 1-bit error.

The error detection circuits FE1 2562 and FE2 2563 together form anerror detection circuit, that generate an error signal on the basis ofthe error syndrome and of the decoder-determined correction signals.

FIG. 26 schematically shows an implementation example of a combinationalcircuit Akomp, which implements the transformation (or compaction) ofthe address bits of the write address a₁, . . . , a₆ in compacted bits

A ₁ , . . . ,A ₄ =F(a ₁ , . . . ,a ₆)=[F ₁(a ₁ , . . . ,a ₆), . . . ,F₄(a ₁ , . . . ,a ₆)].

Hence, l=6 and b=4 is considered in this implementation example.

The compaction is performed in this implementation example according tothe relation

(A ₁ , . . . ,A ₄)^(T) =K·(a ₁ , . . . ,a ₆)^(T)  (15)

with

$\begin{matrix}{{K = \begin{pmatrix}1 & 0 & 0 & 0 & 1 & 1 \\0 & 1 & 0 & 0 & 1 & 1 \\0 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 0 & 1\end{pmatrix}},} & (16)\end{matrix}$

so that

A ₁ =a ₁ ⊕a ₅ ⊕a ₆ =F ₁(a ₁ , . . . ,a ₆)

A ₂ =a ₂ ⊕a ₅ ⊕a ₆ =F ₂(a ₁ , . . . ,a ₆)

A ₃ =a ₃ ⊕a ₅ =F ₃(a ₁ , . . . ,a ₆)

A ₄ =a ₄ ⊕a ₆ =F ₄(a ₁ , . . . ,a ₆).

All columns of the matrix K are pairwise different and have an oddnumber of ones.

The circuitry of FIG. 25 has 6 binary inputs, numbered from 1 to 6, towhich the addresses a₁ to a₆ are provided as inputs and 4 binaryoutputs, numbered from 1 to 4, and via which the compacted bits A₁, A₂,A₃, A₄ are output.

The inputs 1, 5 and 6 are connected, via the XOR gates 2671 and 2673, tothe output 1. The inputs 2, 5 and 6 are connected, via the XOR gates2672 and 2674, to the output 2. The inputs 3 and 5 are connected, viathe XOR gate 2675, to the output 3. The inputs 4 and 6 are connected,via the XOR gate 2676, to the output 4.

In some applications it may be useful that during compacting of theaddress bits in compacted address bits no address is mapped to compactedbits, which are equal to

$\underset{\underset{b}{}}{0,\ldots \mspace{14mu},0}.$

The function F may in this case be chosen such that for all combinationsa₁, . . . , a_(l)ε{0,1}^(l) it holds that

F(a ₁ , . . . ,a _(l))≠0.

It is possible to set a first compacted bit of the compacted b bitsidentical to equal 1 and to compact the address bits a₁, . . . , a_(l)onto the remaining b−1 bits, for example using a (b−1, l)-matrix K⁺ inthe form

(A ₂ , . . . ,A _(b))^(T) =K ⁺·(a ₁ , . . . ,a _(l))^(T).

It is equally possible to derive compacted bits A*₁, . . . , A*_(b) fromalready determined compacted bits A₁, . . . , A_(b), such that the newcompacted bits A*₁, . . . , A*_(b) can never assume the value 0, . . . ,0.

This approach shall be illustrated using an example of 4 compacted bits.

From the four determined compacted bits, which might possible assume thevalue 0,0,0,0, the modified compacted bits A*₁, A*₂, A*₃, A*₄ can beformed according to the relation

A* ₁ A _(1*) =A ₁

A* ₂ A _(2*) =A ₂,

A* ₃ A _(3*) =A ₃,

A* ₄ A _(4*) =A ₄,

so that the following also holds:

A* ₁ A _(1*) =F ₁(a ₁ , . . . ,a ₆)=(a ₁ ⊕a ₅ ⊕a ₆)

A* ₂ A _(2*) =F ₂(a ₁ , . . . ,a ₆)=a ₂ ⊕a ₅ ⊕a ₆,

A* ₃ A _(3*) =F ₃(a ₁ , . . . ,a ₆)=a ₃ ⊕a ₅,

A* ₄ A _(4*) =F ₄(a ₁ , . . . ,a ₆)=a ₄ ⊕a ₆.

A possible implementation of the determination of the modified compactedbits A*₁, A*₂, A*₃, A*₄ is schematically shown in FIG. 27. The circuitryof FIG. 27 has four inputs 1, 2, 3, and 4, to which are applied thecompacted bits A₁, A₂, A₃ and A₄, and four outputs 1, 2, 3, and 4, viawhich the modified compacted bits A*₁, A*₂, A*₃, A*₄ are output.

The input 1 is connected with the first input of an OR gate 2782 withtwo inputs and one output, and also connected with a first input of aNOR gate 2781 with four inputs and an output. The input 2 is connectedwith the output 2 and with a second input of the NOR gate 2781. Theinput 3 is connected with the output 3 and with a third input of the NORgate 2781. The input 4 is connected with the output 4 and the fourthinput of the NOR gate 2781, the output of which is fed into the secondinput of the OR gate 2782. The output of the OR gate 2782 is also theoutput 1 of the circuitry.

In order to achieve that none of the addresses is compacted to acompacted value

$\underset{\underset{b}{}}{0,\ldots \mspace{14mu},0},$

it is possible to set one bit of the compacted bits, for example A₁,constant equal 1. This approach shall be explained for an implementationexample with six address bits a₁, . . . , a₆, which are to be compactedto four bits, of which A₁ is set to A₁=1.

The remaining compacted bits A₂, A₃, A₄ can be determined, for example,according to the relation

(A ₂ ,A ₃ ,A ₄)^(T) =K ⁺·(a ₁ , . . . ,a ₆)^(T)  (17)

with

$\begin{matrix}{K^{+} = {\begin{pmatrix}100110 \\010101 \\001011\end{pmatrix}.}} & (18)\end{matrix}$

All columns of the matrix K⁺ are pairwise different.

The invention is now explained using an actual or realisticimplementation example with 64 data bits u₁, . . . , u₆₄, 8 check bitsc₁, . . . , c₈ and 21 address bits a₁, . . . , a₂₁, which are compactedto 6 compacted bits A₁, . . . , A₆, of which the bit A₁ is set toconstant equal 1.

A shortened Hsiao code C in systematic form is used. All columns of theH matrix of the code C have an odd number of ones.

The code is a 1-bit-error-correcting and 2-bit-error-detecting code.

For address errors an error detection and no error correction isrealized.

First, the address bits a₁, . . . , a₂₁ are compacted to 6 bits 1, A₂, .. . , A₆, wherein for the 5 bits A₂, . . . , A₆ the following holds:

(A ₂ , . . . ,A ₆)^(T) =K ⁺·(a ₁ , . . . ,a ₂₁)^(T).  (19)

In this example, K⁺ is a (5,21)-matrix, the columns of which are allunequal 0 and pairwise different from each other. A constant bit 1 isadjoined to the 5 bits A₂, . . . , A₆. This constant bit 1 results inthat each address a₁, . . . , a₂₁ is mapped to a 6-component vector [1,A₂, . . . , A₆]≠0. Since the columns of K⁺ are all unequal 0 andpairwise different, two different addresses, that differ from each otherin only one bit or two bits, can never be mapped to the same vector 1,A₂, . . . , A₆.

In this manner, all 1-bit and all 2-bit errors in the bits a₁, . . . ,a₂₁ are reliably detected.

The H matrix of the code is the H matrix of a shortened Hsiao-code.

We assume that the generator matrix G of the code is used in itssystematic form. The generator matrix G=(P_(70,8), I₇₀) is then formedby a 70-dimensional identity matrix I₇₀ and a (70,8)-parity matrixP_(70,8). Since the G matrix is used in its systematic form, the databits can be written unchanged in the memory.

The H matrix is also used in its systematic form. The systematic form ofthe H matrix has the benefit that the hardware, which is used for theimplementation of the parity matrix during coding, can also be employedduring decoding for determining the error syndrome.

The H matrix has the form

H=(I ₈ ,P _(8,70) ^(T))=(H ^(c) ,H ^(u) ,H ^(A)) with I ₈ =H ^(c) and P_(8,70) ^(T) =H ^(u) ,H ^(A).  (20)

All columns of the matrix H are unequal 0, pairwise different, and eachcolumn has an odd number of ones.

In the preceding equation

-   -   H^(c)=I₈ is a (8,8)-identity matrix,    -   H^(u) is a (8,64) matrix,    -   H^(A) is a (8,6) matrix.

In particular, the sub-matrix H^(c) (check bits-related sub matrix) hasthe form

$\begin{matrix}{H^{c} = {I_{8} = {\left( {h_{1}^{c},\ldots \mspace{14mu},h_{8}^{c}} \right) = {\begin{pmatrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1\end{pmatrix}.}}}} & (21)\end{matrix}$

The columns of the matrix H^(c) are linearly independent.

The columns h₁ ^(c), . . . , h₈ ^(c) of the matrix H^(c) are chosen sothat

$\begin{matrix}{{{h_{1}^{c} \oplus h_{2}^{c} \oplus \ldots \oplus h_{8}^{c}} = \left\lbrack \underset{\underset{8}{}}{1,\ldots \mspace{14mu},1} \right\rbrack^{T}},} & (22)\end{matrix}$

wherein ⊕ designates the component-wise addition modulo-2.

The matrix H^(A) (compressed address bits-related sub matrix) has theform

$\begin{matrix}{H^{A} = {\left( {h_{1}^{A},\ldots \mspace{14mu},h_{6}^{A}} \right) = {\begin{pmatrix}1 & 1 & 1 & 1 & 1 & 1 \\1 & 1 & 1 & 1 & 1 & 1 \\1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1\end{pmatrix}.}}} & (23)\end{matrix}$

The first two components of each column of the matrix H^(A) are [1,1],i.e., the matrix is constant in these components. The third to eight rowform a 6-dimensional identity matrix.

The matrix H^(u) (user data bits-related sub matrix) with

H ^(u)=(h ₁ ^(u) ,h ₂ ^(u) , . . . ,h ₆₄ ^(u))

has the following properties:

-   -   1. The first two components of h_(i) ^(u), i=1, . . . , 64, are        unequal [1,1] and therefore either equal [0,1], [1,0] or [0,0].    -   2. For i=1, . . . , 64 the number of the components of h_(i)        ^(u), that are equal 1, is either equal 3 or equal 5.    -   3. The matrix H^(u) is determined such that

$\begin{matrix}{{h_{1}^{u} \oplus h_{2}^{u} \oplus \ldots \oplus h_{64}^{u}} = \left\lbrack \underset{\underset{8}{}}{1,\ldots \mspace{14mu},1} \right\rbrack^{T}} & (24)\end{matrix}$

The first 6 columns h₁ ^(u), . . . , h₆ ^(u) of H^(u) are:

$\begin{matrix}{h_{1}^{u},\ldots \mspace{14mu},{h_{6}^{u} = {\begin{matrix}0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 \\1 & 0 & 1 & 0 & 1 & 1 \\1 & 1 & 0 & 1 & 0 & 1 \\1 & 1 & 0 & 1 & 1 & 0 \\0 & 1 & 1 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 0 & 1\end{matrix}.}}} & (25)\end{matrix}$

Each of these 6 columns has 3 ones. It holds:

h ₁ ^(u) ⊕h ₂ ^(u) ⊕h ₃ ^(u) ⊕h ₄ ^(u) ⊕h ₅ ^(u) ⊕h ₆^(u)=[0,0,0,0,0,0,0]^(T)=0.  (26)

The remaining 58 columns h₇ ^(u), . . . , h₆₄ ^(u) of the matrix H^(u)are determined as 29 pairs of successive columns h_(i) ^(u), h_(i+1)^(u), i=7,9,11, . . . , 63 such that h_(i) ^(u) has three componentsthat are equal 1 and h_(i+1) ^(u) has five components that are equal 1.h_(i) ^(u) and h_(i+1) ^(u) are complementary to each other. If the r-thcomponent of h_(i) ^(u) is equal 1, then the r-th component of h_(i+1)^(u) is equal 0. If the r-th component of h_(i) ^(u) is equal 0, thenthe r-th component of h_(i+1) ^(u) is equal 1. The first two componentsof h_(i) ^(u) and h_(i+1) ^(u) are either equal [0,1] or [1,0] andtherefore unequal [1,1]. For the component-wise XOR combination of h_(i)^(u) and h_(i+1) ^(u) we have

h _(u) ^(u) ⊕h _(i+1) ^(u)=[1,1,1,1,1,1,1,1]^(T)

The columns h_(i) ^(u) and h_(i+1) ^(u) are determined based on thefollowing considerations:

-   -   There are

$\begin{pmatrix}6 \\2\end{pmatrix} = 15$

-   -   -   column vectors with eight components in total and with 3            ones, the first two components of which are equal 1,0 and            wherein 2 ones are distributed among the 6 components 3 to            8.

    -   There are

$\begin{pmatrix}6 \\4\end{pmatrix} = 15$

-   -   column vectors with eight components in total and with 5 ones,        the first two components of which are equal 0,1 and wherein 4        ones are distributed among the 6 components 3 to 8.    -   For each vector with 3 ones with the first two components being        1,0 there is exactly one complementary vector with 5 ones and        the first two components 0,1, so that the component-wise XOR-sum        of the vector with 3 ones and its complementary vector with 5        ones equals [1,1,1,1,1,1,1,1]^(T).

In an analogous manner we have:

-   -   There are

$\begin{pmatrix}6 \\2\end{pmatrix} = 15$

-   -   column vectors with eight components in total and with 3 ones,        the first two components of which are equal 0,1 and wherein 2        ones are distributed among the 6 components 3 to 8.    -   There are

$\begin{pmatrix}6 \\4\end{pmatrix} = 15$

-   -   column vectors with eight components in total and with 5 ones,        the first two components of which are equal 1,0 and wherein 4        ones are distributed among the 6 components 3 to 8.    -   For each vector with 3 ones and with the first two components        0,1 there is exactly one complementary vector with 5 ones and        the first two components 1,0, so that the component-wise XOR-sum        of the vector with 3 ones and its complementary vector with 5        ones equals [1,1,1,1,1,1,1,1]^(T).

The 58 columns h₇ ^(u), . . . , h₆₄ ^(u) are chosen as 29 pairs ofcomplementary columns. The first 30 columns consist of 15 first pairs ofcomplementary columns, wherein the first column of each pair is one ofthe 15 column vectors with 3 ones and the first two components 0,1. Theassociated second complementary column is then one of the 15 columnvectors with 5 ones and the first two components 1,0.

The remaining 28 columns consist of 14 second pairs of complementarycolumns, wherein the first column of each of these second pairs is oneof 15 column vectors with 3 ones and the first two components 1,0. Theassociated second complementary column is then one of the 15 columnvectors with 5 ones and the first two components 0,1.

For the component-wise XOR-sum of the 58 columns h₇ ^(u), . . . , h₆₄^(u) or the 29 pairs [h₇ ^(u), h₈ ^(u)], [h₉ ^(u), h₁₀ ^(u)], . . . ,[h₆₃ ^(u), h₆₄ ^(u)] of complementary columns we have

[h ₇ ^(u) ⊕h ₈ ^(u) ]⊕[h ₉ ^(u) ⊕h ₁₀ ^(u) ]⊕ . . . ⊕[h ₆₃ ^(u) ⊕h ₆₄^(u)]=[1,1,1,1,1,1,1,1]^(T)  (27)

from which using equations (22), (24) and (26) it follows

h ₁ ^(c) ⊕ . . . ⊕h ₈ ^(c) ⊕h ₁ ^(u) ⊕ . . . ⊕h ₆ ^(u) ⊕h ₇ ^(u) ⊕ . . .⊕h ₆₄ ^(u)=0  (28)

and therefore

$\begin{matrix}{{\left( {H^{c}H^{x}} \right) \cdot \left( \underset{\underset{72}{}}{1,\ldots \mspace{14mu},1} \right)} = 0.} & (29)\end{matrix}$

Next the error correction and error detection properties of thepreceding implementation example are described.

The H matrix H is, as previously explained, a H matrix of a shortenedHsiao code, and all columns of the H matrix have an odd number of ones.

For the data bits and the check bits we have:

-   -   Each 1-bit error results in an error syndrome that has an odd        number of ones and that is equal [0,0], [1,0] or [0,1] in the        first two components.    -   A 2-bit error in the data bits and/or check bits results in an        error syndrome ≠0, that has an even number of ones. An error        syndrome unequal 0 with an even number of ones is indicated as a        non-correctable error.        For the address bits we have in summary:    -   address errors have an error syndrome that is either equal [1,1]        or equal [0,0] in the first two components.

In case the error syndrome is equal [1,1] in the first two components,then it differs from the error syndrome of an arbitrary 1-bit error inthe data bits and check bits, that is either equal [0,0], [1,0] or [0,1]in the first two components. It is indicated as a non-correctable errorand detected in a reliable manner.

In case the first two bits of the error syndrome of an address error areequal [0,0], then the number of the components that are equal 1 is even.Since a 1-bit error in the data bits and check bits presents an oddnumber of ones, the address error is detected as a non-correctable errorwhen the error syndrome is ≠0.

These statements are now explained more in detail.

The modification of the compressed (compacted) address values ΔA₂, . . ., ΔA₆ is defined by

ΔA ₂ , . . . ,ΔA ₆ =A ₂ ⊕A ₂ ^(f) , . . . ,A ₆ ⊕A ₆ ^(f).  (30)

[A₂, . . . , A₆]^(T)=K⁺·[a₁, . . . , a₂₁]^(T) are the compacted valuesof the correct address bits and [A₂ ^(f), . . . , A₆ ^(f)]^(T)=K^(T)·[a₁^(f), . . . , a₂₁ ^(f)]^(T)[A₂, . . . , A₆]^(T)=K⁺·[a₁, . . . ,a₂₁]^(T)[A₂ ^(f), . . . , A₆ ^(f)]^(T)=K^(T). [a₁ ^(f), . . . , a₂₁^(f)]^(T) the compacted values of the erroneous address bits. Thesyndrome resulting from an address error S(A) is

$\begin{matrix}\begin{matrix}{{S(A)} = {{H^{A} \cdot \left\lbrack {0,{\Delta \; A_{2}},{\Delta \; A_{3}},{\Delta \; A_{4}},{\Delta \; A_{5}},{\Delta \; A_{6}}} \right\rbrack^{T}} =}} \\{= \begin{pmatrix}{{\Delta \; A_{2}} \oplus {\Delta \; A_{3}} \oplus {\Delta \; A_{4}} \oplus {\Delta \; A_{5}} \oplus {\Delta \; A_{6}}} \\{{\Delta \; A_{2}} \oplus {\Delta \; A_{3}} \oplus {\Delta \; A_{4}} \oplus {\Delta \; A_{5}} \oplus {\Delta \; A_{6}}} \\0 \\{\Delta \; A_{2}} \\{\Delta \; A_{3}} \\{\Delta \; A_{4}} \\{\Delta \; A_{5}} \\{\Delta \; {A_{6}.}}\end{pmatrix}}\end{matrix} & (31)\end{matrix}$

Every address error for which holds ΔA₂, . . . , ΔA₆≠0,0,0,0,0, resultsin a syndrome unequal 0.

If the number of ones in ΔA₂, . . . , ΔA₆ is odd, then the first twocomponents of S(A) are equal [1,1], and the address error is detected asnon-correctable error. If the number of ones in ΔA₂, . . . , ΔA₆ is evenand if ΔA₂, . . . , ΔA₆≠0,0,0,0,0, then the number of the components ofS(A) that are equal 1 is even so that the error is detected asnon-correctable error.

If ΔA₂, . . . , ΔA₆=0,0,0,0,0, although an address error exists in theaddress bits a₁, . . . , a₂₁, then the error is not detected. This caseoccurs very seldom.

It may be of interest that two special errors, in which all memory cellsassume the value 0 or all memory cells assume the value 1, are reliablydetected independent from the value of the address.

In case all memory cells assume the value 0, then this is typicallycalled an All-0 error. In case all memory cells assume the value 1, thenthis is typically called an All-1 error.

In other words, if all memory cells have the value 0, then an All-0error has occurred (is present). Since the address bits and thecompacted address bits are not stored, an All-0 error means that alldata bits and check bits are equal 0 and the compacted address bits A₂,. . . , A₆ can assume arbitrary values, including

$\underset{\underset{5}{}}{0,\ldots \mspace{14mu},0}.$

If all memory cells have the value 1, then an All-1 error has occurred(is present). Since the address bits and the compacted address bits arenot stored, an All-1 error means that all data bits and check bits areequal 1 and the compacted address bits A₂, . . . , A₆ can assumearbitrary values, including

$\underset{\underset{5}{}}{0,\ldots \mspace{14mu},0}.$

We now determine the error syndrome S(All-0) for an All-0 error. We have

$\begin{matrix}\begin{matrix}{{s\left( {{All} - 0} \right)} = {\left( {H^{c},H^{u},H^{A}} \right) \cdot \left\lbrack {\underset{\underset{72}{}}{0,\ldots \mspace{14mu},0},1,A_{2},\ldots \mspace{14mu},A_{6}} \right\rbrack^{T}}} \\{= {H^{A} \cdot \left\lbrack {1,A_{2},\ldots \mspace{14mu},A_{6}} \right\rbrack^{T}}} \\{= {\begin{bmatrix}{1 \oplus A_{2} \oplus A_{3} \oplus A_{4} \oplus A_{5} \oplus A_{6}} \\{1 \oplus A_{2} \oplus A_{3} \oplus A_{4} \oplus A_{5} \oplus A_{6}} \\1 \\A_{2} \\A_{3} \\A_{4} \\A_{5} \\{A_{6}.}\end{bmatrix}.}}\end{matrix} & (32)\end{matrix}$

At the same time we have

[A ₂ , . . . ,A ₆]^(T) =K ⁺ ·[a ₁ , . . . ,a ₂₁]^(T).

If the number of the values A₂, . . . , A₆ that are equal 1 is odd, thenthe first two components of the error syndrome S (All-0) are equal [0,0]and the error syndrome presents an even number of ones. In this mannerthe error All-0 is detected as a non-correctable error. If the number ofthe values A₂, . . . , A₆ that are equal 1 is even, then the first twocomponents of the error syndrome s(All 0) are equal [1,1]. In thismanner the error All-0 is detected as a non-correctable error.

Irrespective of the value of the address bits, All-0 is detected as anon-correctable error.

We now determine the error syndrome S(All-1) for an All-1 error. We have

$\begin{matrix}\begin{matrix}{{S\left( {{All} - 1} \right)} = {\left( {H^{c},H^{u},H^{A}} \right) \cdot \left\lbrack {\underset{\underset{72}{}}{1,\ldots \mspace{14mu},1},1,A_{2},\ldots \mspace{14mu},A_{6}} \right\rbrack^{T}}} \\{= {H^{A} \cdot \left\lbrack {1,A_{2},\ldots \mspace{14mu},A_{6}} \right\rbrack^{T}}} \\{= {\begin{bmatrix}{1 \oplus A_{2} \oplus A_{3} \oplus A_{4} \oplus A_{5} \oplus A_{6}} \\{1 \oplus A_{2} \oplus A_{3} \oplus A_{4} \oplus A_{5} \oplus A_{6}} \\1 \\A_{2} \\A_{3} \\A_{4} \\A_{5} \\{A_{6}.}\end{bmatrix}.}}\end{matrix} & (33)\end{matrix}$

Care has been taken that the columns of H^(c) and H^(u) have beendetermined that

${\left( {H^{c},H^{u}} \right) \cdot \left\lbrack \underset{\underset{72}{}}{1,\ldots \mspace{14mu},1} \right\rbrack} = {\underset{\underset{8}{}}{0,\ldots \mspace{14mu},0}.}$

If the number of the values A₂, . . . , A₆ that are equal 1 is odd, thenthe first two components of the error syndrome S(All-1) are equal [0,0]and the error syndrome has an even number of ones. In this manner All-1is detected as a non-correctable error. If the number of the values A₂,. . . , A₆ that are equal 1 is even, then the first two components ofthe error syndrome S(All-1) are equal [1,1]. In this manner an All-1 isdetected as an uncorrectable error.

Irrespective of the value of the address bits, All-1 is detected as anuncorrectable error.

The functionality of the error detection and correction will beexplained subsequently using actual examples for 64 data bits, 8 checkbits and 21 address bits. The code C that is used, is constructed viaits H matrix H. The sub matrices H^(c) and H^(A), as well as the first 6column vectors of the Matrix H^(u) are already given by the equations(21), (23) and (25). The remaining 58 column vectors of the Matrix H^(u)are chosen according to the description above as 29 pairs ofcomplementary column vectors. The H matrix H of the code C can beselected according to

$\begin{matrix}{H = {\begin{pmatrix}10000000 & 0000001010101010101010101010101010100101010101010101010101010101 & 111111 \\01000000 & 0000000101010101010101010101010101011010101010101010101010101010 & 111111 \\00100000 & 1010110101010101010101010110101010100101010101010101010110101010 & 100000 \\00010000 & 1101010101010101011010101001010101100101010101011010101001010101 & 010000 \\00001000 & 1101100101011010100101011001010110010101011010100101011001010110 & 001000 \\00000100 & 0110000110100101100101100101011001010110100101100101100101011001 & 000100 \\\underset{\underset{H^{c}}{}}{00000010} & \underset{\underset{H^{u}}{}}{0010101001100110010110010101100101011001100110010110010101100101} & \underset{\underset{H^{A}}{}}{000010}\end{pmatrix}.}} & (34)\end{matrix}$

The sub matrices H^(u), H^(A) form the transposed P_(8,70) ^(T) of theparity matrix P_(70,8) of the code C:

$\begin{matrix}{P_{8,70}^{T} = {\begin{pmatrix}0000001010101010101010101010101010100101010101010101010101010101 & 111111 \\0000000101010101010101010101010101011010101010101010101010101010 & 111111 \\1010110101010101010101010110101010100101010101010101010110101010 & 100000 \\1101010101010101011010101001010101100101010101011010101001010101 & 010000 \\1101100101011010100101011001010110010101011010100101011001010110 & 001000 \\0110000110100101100101100101011001010110100101100101100101011001 & 000100 \\\underset{\underset{H^{u}}{}}{0010101001100110010110010101100101011001100110010110010101100101} & \underset{\underset{H^{A}}{}}{000010}\end{pmatrix}.}} & (35)\end{matrix}$

The parity matrix can be obtained from P_(8,70) ^(T) by transposing:

P _(70,8)=(P _(8,70) ^(T))^(T)  (36)

The parity matrix P_(70,8) of the example code is represented inequation (37). One obtains P_(70,8) from P_(8,70) ^(T) by interchanging(“swapping”) the rows and the columns.

In the contemplated implementation examples 64 data bits u₁, . . . , u₆₄are to be stored in the memory under the address a₁, . . . , a₂₁. Forforming the 8 check bits associated with the 64 data bits, in a firststep the 21 address bits a₁, . . . , a₂₁ are compacted on the basis ofthe matrix K⁺ to 6 bits A₁, . . . , A₆. The (5,21) matrix K⁺ can bechosen, according to at least some aspects of the invention, as follows:

$\begin{matrix}{K^{+} = {\begin{pmatrix}100001111000000111111 \\010001000111000111000 \\001000100100110100110 \\000100010010101010101 \\000010001001011001011\end{pmatrix}.}} & (38)\end{matrix}$

All columns of the matrix K⁺ are unequal 0 and pairwise different.

The compacted address bits A₂, . . . , A₆ of the write address areformed due to (19) according to the relation

(A ₂ , . . . ,A ₆)^(T) =K ⁺·(a ₁ , . . . ,a ₂₁)^(T)

and the compacted bit A₁ is set to A₁=1. The check bits c₁, . . . , c₈to be written are generated as a function of the data bits and thecompacted address bits using the parity matrix P_(70,8):(c₁, . . . , c₈, u₁, . . . , u₆₄, A₁, . . . , A₆)·H^(T)=0(c₁, . . . ,c₈)=(u₁, . . . , u_(q), A₁, . . . , A₆)·P_(70,8)·(c₁, . . . , c₈, u₁, .. . , u₆₄, A₁, . . . , A₆) is a codewort of the systematic code C and itholds that

(c ₁ , . . . ,c ₈ ,u ₁ , . . . ,u ₆₄ ,A ₁ , . . . ,A ₆)·H ^(T)=0

The check bits and the data bits are stored in memory under the addressa₁, . . . , a₂₁.

It is possible that the check bits and the data bits stored in memoryand also the address bits are erroneous.

If the values c₁, . . . , c₈, u₁, . . . , u₆₄, 1, A₂, . . . , A₆ differfrom the values c′₁, . . . , c′₈, u′₁, . . . , u′₆₄, 1, A′₂, . . . ,A′₆, then typically an error has occured.

An error can be described by an error vector

f=(f ₁ ^(c) , . . . ,f ₈ ^(c) ,f ₁ ^(u) , . . . ,f ₆₄ ^(u) ,f ₁ ^(A) , .. . ,f ₆ ^(A))=(c ₁ ⊕c′ ₁ , . . . ,c ₈ ⊕c′ ₈ ,u ₁ ⊕u′ ₁ , . . . ,u ₆₄⊕u′ ₆₄,1⊕1,A ₂ ⊕A′ ₂ , . . . ,A ₆ ⊕A′ ₆).

If

${f = \left( \underset{\underset{78}{}}{0,\ldots \mspace{14mu},0} \right)},$

then typically no error has occurred. If

${f \neq \left( \underset{\underset{78}{}}{0,\ldots \mspace{14mu},0} \right)},$

then an error has occurred. The error syndrome S_(f) of an error f is

S _(f)=(S ₁ , . . . , S ₈)^(T=) H·f ^(T)

For explaining the mode of operation of the invention, we contemplatefirst the case that the 7-th data bit u′₇ is erroneous and that allother bits are not erroneous. We assume that the read address a′₁=a₁, .. . , a′₂₁=a₂₁ is equal to the write address and thus also the compactedaddress bits of the read address are equal to the compacted bits of thewrite address.

The error vector is then

${f = \left( {\underset{\underset{8}{}}{0,\ldots \mspace{14mu},0},\underset{\underset{6}{}}{0,\ldots \mspace{14mu},0},1,\underset{\underset{57}{}}{0,\ldots \mspace{14mu},0},\underset{\underset{6}{}}{0,\ldots \mspace{14mu},0}} \right)},$

and the error syndrome s_(f) is

s _(f) ^(T) =H·f ^(T)=(10000011)^(T).

The error syndrome is equal to the 7-th column of the matrix H^(u).Since s_(f)≠0 and has an odd number of ones, a correction signal e₇^(u)=1 is generated by the decoder Dec 2561. No further correctionsignals ≠0 are output by the decoder. The corrected 7-th data bit u₇^(cor) is then u₇ ^(cor)=u′₇⊕e₇ ^(u)=x′₇⊕1= u′ ₇. No further bits arecorrected.

The error syndrome s_(f) presents an odd number of ones and for thefirst two components we have s₁, s₂≠1,1. Furthermore, the syndrome scorresponds to the 15-th column of the matrix H, that is to columnvector that corresponds to the 7-th data bit. The decoder determinescorrection signals of the form

e ₁ , . . . ,e ₇₂ =e ₁ ^(c) , . . . ,e ₈ ^(c) ,e ₁ ^(u) , . . . ,e ₆₄^(u)

to the check bits and the data bits on the basis of the error syndromes, wherein e_(i) ^(c)=0 for i=1, . . . , 8, e_(j) ^(u)=0 for j=1, . . ., 6,8, . . . , 64 and e₇ ^(u)=1.

The check bits and the data bits to be corrected are then combined withthe corresponding correction signals to yield the corrected check bitsand data bits:

$\left( {c_{1}^{cor},\ldots \mspace{14mu},c_{8}^{cor},u_{1}^{cor},\ldots \mspace{14mu},u_{64}^{cor}} \right) = {{\left( {c_{1}^{\prime},\ldots \mspace{14mu},c_{8}^{\prime},u_{1}^{\prime},\ldots \mspace{14mu},u_{64}^{\prime}} \right) \oplus \left( {e_{1}^{c},\ldots \mspace{14mu},e_{8}^{c},e_{1}^{u},\ldots \mspace{14mu},e_{64}^{u}} \right)} = {{\left( {c_{1},\ldots \mspace{14mu},c_{8},u_{1},\ldots \mspace{14mu},u_{6},\overset{\_}{u_{7}},u_{8},\ldots \mspace{14mu},u_{64}} \right) \oplus \left( {\underset{\underset{14}{}}{0,\ldots \mspace{14mu},0},1,\underset{\underset{57}{}}{0,\ldots \mspace{14mu},0}} \right)} = {\left( {c_{1},\ldots \mspace{14mu},c_{8},u_{1},\ldots \mspace{14mu},u_{6},u_{7},u_{8},\ldots \mspace{14mu},u_{64}} \right).}}}$

We now consider the case that the 5-th check bit c′₅ and the 29-th databit u′₂₉ are erroneous. It is assumed that no further errors arepresent.

The error vector f is then

${f = \left( {00001000\mspace{20mu} \underset{\underset{28}{}}{0,\ldots \mspace{11mu},0}\mspace{11mu} 1\mspace{11mu} \underset{\underset{35}{}}{0,\ldots \mspace{11mu},0}\mspace{11mu} \underset{\underset{6}{}}{0,\ldots \mspace{11mu},0}} \right)},$

and the error syndrome s_(f) is

S _(f) ^(T) =H·f ^(T)=(10101010)^(T),

which corresponds to the component-wise XOR-sum of the 5-th column(00001000)^(T) of the matrix H^(c) and the 29-th column (10100010)^(T)of the matrix Hu. The error syndrome S_(f) is unequal 0, and has an evennumber of ones. A non correctable error is indicated.

We now describe the mode of operation of the invention for a firstaddress error. Let us consider the case in which the read address a′₁,a₂₁′ differs from the write address a₁, . . . , a₂₁ in the 13-th bit,i.e., a′₁₃≠a₁₃. It is assumed that no further error has occurred. Wehave

${\left( {{\Delta \; A_{2}},\ldots \mspace{11mu},{\Delta \; A_{6}}} \right)^{T} = {\left\lbrack {K^{+} \cdot \left( {a_{1},\ldots \mspace{11mu},a_{21}} \right)^{T}} \right\rbrack \oplus {\left\lbrack {K^{+} \cdot \left( {a_{1\prime},\ldots \mspace{11mu},a_{21}^{\prime}} \right)^{T}} \right\rbrack a_{1}^{\prime}}}},\ldots \mspace{11mu},{{a_{21}^{\prime}\left( {{\Delta \; A_{2}},\ldots \mspace{11mu},{\Delta \; A_{6}}} \right)}^{T} = {{\left\lbrack {K^{+} \cdot \left( {a_{1},\ldots \mspace{11mu},a_{21}} \right)^{T}} \right\rbrack \oplus \left\lbrack {K^{+} \cdot \left( {a_{1\prime},\ldots \mspace{11mu},a_{21}^{\prime}} \right)^{T}} \right\rbrack} = {{K^{+} \cdot \left( {{a_{1} \oplus a_{1\prime}},\ldots \mspace{11mu},{a_{21} \oplus a_{21}^{\prime}}} \right)^{T}} = {{K^{+} \cdot \left( {\underset{\underset{12}{}}{0,\ldots \mspace{11mu},0},1,\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0}} \right)^{T}}a_{1}^{\prime}}}}},\ldots \mspace{11mu},{a_{21}^{\prime} = {{K^{+} \cdot \left( {{a_{1} \oplus a_{1\prime}},\ldots \mspace{11mu},{a_{21} \oplus a_{21}^{\prime}}} \right)^{T}} = {{K^{+} \cdot \left( {\underset{\underset{12}{}}{0,\ldots \mspace{11mu},0},1,\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0}} \right)^{T}} = \left( {0,0,1,1,0} \right)^{T}}}},$

and the address error affects the compacted address bits in a mannerthat 1, A′₂, . . . , A′₆ differs from 1, A₂, . . . , A₆ by 0,0,0,1,1,0and ΔA₁, ΔA₂, . . . , ΔA₆=0,0,0,1,1,0. The constant value A₁=A′₁=1 cannot be erroneous.

The error vector f is

${f = \left( {\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0},\underset{\underset{64}{}}{0,\ldots \mspace{11mu},0},0,0,0,1,1,0} \right)},$

and the error syndrome S_(f) is then

$S_{f}^{T} = {{H \cdot \left( {\underset{\underset{8}{}}{0,\ldots \;,0},\underset{\underset{64}{}}{0,\ldots \;,0},0,0,0,1,1,0} \right)^{T}} = {\left( {0,0,0,0,0,1,1,0} \right)^{T}.}}$

The error syndrome S_(f) is equal to the component-wise XOR-sum of thefourth column (1,1,0,0,0,1,0,0)^(T) and the fifth column(1,1,0,0,0,0,1,0)^(T) of H^(A). Since the error syndrome s_(f) isunequal 0 and has an even number of ones, the address error is detectedas a non-correctable error.

Now a second address error shall be considered. According to this errorthe read address and the write address differ in the 8-th and in the18-th bit, i.e. a′₈≠a₈ and a′₁₈≠a₁₈. No further errors are assumed.

We now have

${\left( {{\Delta \; A_{2}},\ldots \mspace{11mu},{\Delta \; A_{6}}} \right)^{T} = {\left\lbrack {K^{+} \cdot \left( {a_{1},\ldots \;,a_{21}} \right)^{T}} \right\rbrack \oplus {\left\lbrack {K^{+} \cdot \left( {a_{1\prime},\ldots \;,a_{21}^{\prime}} \right)^{T}} \right\rbrack a_{1}^{\prime}}}},\ldots \mspace{11mu},{{a_{21}^{\prime}\left( {{\Delta \; A_{2}},\ldots \mspace{11mu},{\Delta \; A_{6}}} \right)}^{T} = {{\left\lbrack {K^{+} \cdot \left( {a_{1},\ldots \;,a_{21}} \right)^{T}} \right\rbrack \oplus \left\lbrack {K^{+} \cdot \left( {a_{1\prime},\ldots \;,a_{21}^{\prime}} \right)^{T}} \right\rbrack} = {{K^{+} \cdot \left( {{a_{1} \oplus a_{1\prime}},\ldots \mspace{11mu},{a_{21} \oplus a_{21}^{\prime}}} \right)^{T}} = {{K^{+} \cdot \left( {\underset{\underset{12}{}}{0,\ldots \;,0},1,\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0}} \right)^{T}}a_{1}^{\prime}}}}},\ldots \mspace{11mu},{a_{21}^{\prime} = {\left\lbrack {K^{+} \cdot \left( {{a_{1} \oplus a_{1\prime}},\ldots \;,{a_{21} \oplus a_{21}^{\prime}}} \right)^{T}} \right\rbrack = {{K^{+} \cdot \left( {\underset{\underset{7}{}}{0,\ldots \mspace{11mu},0},1,\underset{\underset{9}{}}{0,\ldots \mspace{11mu},0},1,0,0,0,} \right)^{T}} = {\left( {0,1,0,1,1} \right)^{T}.}}}}$

The compacted address bits 1, A′₂, . . . , A′₆ of the read addressdiffer from the compacted address bits 1, A₂, . . . , A₆ of the writeaddress by 0,0,1,0,1,1.

The error vector f is

$f = \left( {\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0},\underset{\underset{64}{}}{0,\ldots \mspace{11mu},0},0,0,1,0,1,1} \right)$

and the error syndrome S_(f) is

$S_{f}^{T} = {{H \cdot \left( {\underset{\underset{8}{}}{0,\ldots \mspace{11mu},0},\underset{\underset{64}{}}{0,\ldots \mspace{11mu},0},0,0,1,0,1,1} \right)^{T}} = {\left( {1,1,0,0,1,0,1,1} \right)^{T}.}}$

and it is equal to the component-wise XOR-sum of the third, fifth andsixth column of the matrix H^(A).

Since the first two components of S_(f) ^(T) are equal 1,1 and the errorsyndrome of each 1-bit error in the data bits or the check bits in thefirst two components is unequal 1,1, the address error(s) is detected asuncorrectable error.

FIGS. 28-37 relate to an alternative solution according to which an atleast 2-bit error correcting code (i.e. a t-bit error correcting code,with t≧2) for the information bits and the check bits is combined withan address error detection having a high detection probability, e.g.,higher than 99% or even higher than 99.9%.

In order to achieve an address error detection with about 99.9%, a newcode is proposed for error correction of t-bit errors in the data bitsand check bits and very high error detection probability for arbitraryaddress errors. Detection of address errors with 99.9% can now beachieved with much less check bits as it is possible until now.

In memories, it may be desired to correct t-bit errors and to detectmulti-bit errors, e.g., for t=2. Of special importance are addresserrors with potentially catastrophic consequences. Address errors haveto be detected with very high probability. In a currently used design(internal knowledge of the assignee), address errors may be detectedwith 98.8% by use of 21 check bits, but a higher probability is desired.

Errors may be corrected and detected by use of their error syndromes. Anerror is typically mapped to an error syndrome, and the error syndromedetermines what type of error occurred and whether it can be corrected,or only detected. For a code length of n there are 2^(n)−1 arbitraryerrors. If the syndrome has m components, there are only 2^(m) errorsyndromes and in general 2^(n−m) errors are mapped to each syndrome.

If an arbitrary error which is not a t-bit error is mapped to a syndromecorresponding to a t-bit error, when t-bit errors are corrected, thenthe arbitrary error is miscorrected. This is one of the reasons for therelatively high miscorrection rate of arbitrary errors if the code isused for error correction of t-bit errors with t≧1, for example, for theabove mentioned design currently used within the assignee.

According to what will be described in more detail below with respect toFIGS. 28-37, the parity check matrix of the proposed code is constructedsuch that arbitrary address errors are never mapped to syndromes of1-bit, 2-bit, . . . t-bit errors. The construction is possible for t≧2.Only if an address-multi-bit error is mapped to the syndrome 0 (syndromeof no error) then it cannot be detected. This occurs only on one out of2^(m) cases and therefore the error detection probability for addresserrors is extremely high.

As an example, for a currently contemplated new design with 256 databits and 21 check bits, >99.9% detection probability for address errorscan be achieved, as compared to 98.8% detection probability that couldbe achieved with preceding designs. This result can be achieved by asyndrome generator that implements a parity matrix with specialproperties, as will be explained below.

It is known to a person skilled in the art to detect and to correcterrors in a sequence of bits by error-detecting and error-correctingcodes. For example, k data bits or information bits u=u₁, . . . , u_(k)may be supplemented by m check bits c=c₁, . . . , c_(m), so that thebits v₁, . . . , v_(n)=c₁, . . . , c_(m), u₁, . . . , u_(k) form acodeword of a code C.

It is also possible to add the check bits of the right side to theinformation bits. Then, u₁, . . . , u_(k), c₁, . . . , c_(i) is acodeword of the considered code.

Since the unmodified information bits are bits of a codeword, the codeis called a systhematic code.

The invention is not restricted to systematic codes. Also,non-systhematic codes can be used.

If the code C is a linear systhematic or non-systhematic linear code,then a codeword v may be determined from the information bits by

v=u·G

wherein G is the generator matrix of the code. G may be either insysthematic or in non-systhematic form as it is known to an ordinaryexpert in this field.

A G-matrix in non-systhematic form can be always transformed into aG-matrix in systhematic form by component-wise XOR-combining of rows andby permuting columns of the G-matrix in non-systhematic form.

On the other hand, a G-matrix in its systhematic form can also betransformed in arbitrarily given non-systhematic form of the code bycomponent-wise XOR-combining the rows and by permuting the columns ofthe G-matrix in its systhematic form.

Since it is often advantageous to store data unmodified in the memory,which is possible if the codes are used in their systhematic form, theinvention is described mainly by examples with the codes in theirsysthematic form.

Of course, the invention can also be used, if the considered code is anon-systhematic code.

If C is a linear code, then a codeword v may be determined by

v=u·G,

wherein G is the generator matrix of the code, G is here a (k, n) matrixwith n−k=m.

A codeword v=v₁, . . . , v_(n) may be changed by errors into anerroneous word v′=v′₁, . . . , v′_(n). An error may be described by anerror vector. The error vector e=e₁, . . . , e_(n) is defined by

e=e ₁ , . . . ,e _(n) =v ₁ ⊕v′ ₁ , . . . ,v _(n) ⊕v′ _(n).

If the i-th component e, of the error vector e is equal to 1, v_(i) andv′_(i) are different and an error exists in the i-th bit. If e_(i)=0,v_(i) and v′_(i) are not different and there is no error in the i-thbit.

The error syndrome s of a sequence v′=v′₁, . . . , v′_(n) is determinedby

S ^(T) =H·[v′ ₁ , . . . ,v′ _(n)]^(T) =H·[e ₁ , . . . ,e _(n)]^(T).

Here, H is the H matrix or parity check matrix of the code C and S^(T)is the transposed vector of the row vector S=S₁, . . . , S_(m). Hence,S^(T) is a column vector. Likewise, [v′₁, . . . , v′_(n)]^(T) and [e₁, .. . , e_(n)]^(T) designate the transposed column vectors of the rowvectors v′ and e. The matrix H here is a m,n-matrix.

Note that in the above equation the erroneous code word v′ can be splitup as the sum of the corresponding (error-free) code word v and thecorresponding error vector e. The syndrome of an (error-free) code wordis 0, so that the syndrome of the erroneous codeword v′ is equal to thesyndrome of the corresponding error vector e, as demonstrated in theabove equation.

The error syndrome S may be determined by a syndrome generator from thebits v′₁, . . . , v′_(n). For linear codes, the syndrome generator maybe a combinational circuit with n inputs and m outputs, into which thebits v′₁, . . . , v′_(n) are input and which outputs the associatederror syndrome S. The syndrome generator may be realized using XORgates.

If all components of the error vector e are equal to 0, no error ispresent and v′=v applies. For a code vector, v′=v applies and the errorsyndrome is equal to 0|^(T), wherein 0| here designates an m-componentcolumn vector whose components are all 0 (accordingly its transpose0|^(T) designates an m-component row vector).

If exactly one component of the error vector e is equal to 1, a 1-biterror exists. If exactly t components of the error vector e are equal to1, then a t-bit error exists.

If the code C is a t-bit error correcting code with t≧1, then the errorsyndromes of all 1-bit to t-bit errors are pair-wise different and basedon the existing syndrome it may be determined by a decoder which bitsare to be corrected. In principle, this is easily possible using atable, which is, however, often elaborate for realistic word widths,which is why special correction methods have been developed for thedifferent codes. The correction of bits may take place by XOR-ing thebit to be corrected with the correction value.

The decoder and the corresponding XOR-combinations may be combined toform a corrector. If negated values of the bits or of the correctionvalues are used, the combinations of the bits to be corrected and thecorrection values may be implemented by XNOR gates.

If the code C is a T-bit error detecting code with T≧1, then the errorsyndromes of all 1-bit to T-bit errors are unequal to 0 and each 1-bitto T-bit error unequal 0 may be differentiated from a correct codewordby the fact that the error syndrome corresponding to the same is ≠0|.

An example for a 1-bit error correcting code is the Hamming code and aknown example for a 1-bit error correcting and 2-bit error detectingcode is the Hsiao code.

Examples for t-bit error correcting codes for t≧2 are the BCH codes, forexample described in the textbook by Lin, S. And Costello, D. “ErrorControl Coding, Fundamentals and Applications” Prentice Hall, pp.141-170, 1983. Apart from that, reference is further to be made to thepaper by Okano, H. And Imai, K. “A construction method of high-speeddecoders using ROM's for Bose-Chaudhuri Hocqenhem and Reed Solomoncodes” IEEE trans. Comp C 36, pp. 1165-1171, 1987.

For a first embodiment, FIG. 28 shows a syndrome generator Synd 110having an n-bit wide input for inputting an n-bit wide binary wordv′=v′₁, . . . , v′_(n) and having an m-bit wide output connected to anm-bit wide input of a subcircuit Cor/Det 120 for correcting erroneousbits and for detecting errors comprising a first k-bit wide output foroutputting a correction vector e^(cor) and a second R-bit wide outputfor outputting an R-bit wide error signal E, wherein R≧1.

The syndrome generator Synd 110 is implemented so that it forms anor-bit wide error syndrome s=S₁, . . . , s_(m) according to thefollowing relation

S ^(T) =H·(v′)^(T)  (39)

Here, H is the H matrix (parity check matrix) of the considered linearcode C. H is an (m, n) matrix, wherein m is the number of check bits ofthe code C and n is the length of the code.

The column vector S^(T) designates the transposed vector of the rowvector S=S₁, . . . , S_(mL). Accordingly, (v′)^(T) designates thetransposed vector of the row vector v′.

The H matrix H of the code C comprises a first sub-matrix H^(x) which isa (m, k) matrix, and a second sub-matrix H^(a) which is an (m, l)matrix, so that the following applies

H=(H ^(x) ,H ^(a)).  (40)

The sub-matrix H^(a) may also be referred to as H^(y). The letter “x”when used as an exponent or index may be understood as relating to partsof the code word for which an error correction is intended (up to t-biterrors), and the letter “y” as exponent or index may be understood asrelating to parts of the code word for which an error detection isintended (depending on the embodiment, up to the entire length said partof the code word, i.e., up to l bits).

Here v′=v′₁, . . . , v′_(n)=x′₁, . . . , x′_(k+m), a′₁, . . . , a′_(l)with x′=x′₁, . . . , x′_(k+m) and y′=y′₁, . . . , y′_(l) is an n digitbinary word with n=k+m+l which resulted from a codeword v=v₁, . . . ,v_(n)=x₁, . . . , x_(k+m), y₁, . . . , y_(l) of the considered code Cdue to errors. Note that the vector x′=x′₁, . . . , x′_(k+m) correspondsto the combination or concatenation of the possibly erroneousinformation bits u′=u′₁, . . . , u′_(k) and the check bits c′=c′₁, . . ., c′_(m) shown in, for example, FIGS. 2-8 and described in thecorresponding description.

If no error exists and if v′=v=x₁, . . . , x_(k+m), a₁, . . . , a_(l) isa codeword of a code C, then the error syndrome S determined by equation(39) is equal to 0.

If v′=x′₁, . . . , x′_(k+m), a′₁, . . . , a′_(l)≠x₁, . . . , x_(k+m),a₁, . . . , a_(l), wherein x₁, . . . , x_(k+m), a₁, . . . , a_(l) is acodeword of a code C, then it is possible that the subcircuit Cor/Det120 corrects errors and/or detects errors.

It is here provided in the circuitry in FIG. 28 that errors in the bitsx′₁, . . . , x′_(k+m) which comprise at most t erroneous bits arecorrected, wherein t≧2 applies and errors in the bits a′₁, . . . ,a′_(l) are detected.

The syndrome generator Synd 110 is configured so that it outputs adifferent error syndrome for each 1-bit to t-bit error in the bits x′₁,. . . ,x′_(k+m), so that the error syndromes output by the syndromegenerator Synd 110 are different pair-wise for all 1-bit to t-bit errorsin the bits x′₁, . . . , X′_(k+m).

Apart from that, the syndrome generator Synd 110 is configured so thatfor any random error in the bits a′₁, . . . , a′_(l), i.e. for anyrandom 1-bit, 2-bit, . . . , l-bit error in the bits a′₁, . . . , a′_(l)it outputs an error syndrome which is different from all error syndromesoutput by the syndrome generator Synd 110 in case of a 1-bit to t-biterror in the bits x′₁, . . . , x′_(k+m). If an error exists in the bitsx′₁, . . . , x′_(k+m) and if the bits a₁=a′₁, . . . , a_(l)=a′_(l) arecorrect, it may be described by an error vector

$\begin{matrix}{{e^{x} = {x_{1} \oplus x_{1}^{\prime}}},\ldots \mspace{11mu},{x_{k + m} \oplus x_{k + m}^{\prime}},{a_{1} \oplus a_{1}^{\prime}},\ldots \mspace{11mu},{{a_{l} \oplus a_{l}^{\prime}} = e_{1}^{x}},\ldots \mspace{11mu},x_{k + m}^{x},\underset{\underset{i}{}}{0,\ldots \;,0}} & (31)\end{matrix}$

If an error exists in the bits a′₁, . . . , a′_(l) and if the bitsx₁=x′₁, . . . , x_(k+m)=x′_(k+m) are correct, it may be described by anerror vector

$\begin{matrix}{{e^{a} = {x_{1} \oplus x_{1}^{\prime}}},\ldots \;,{x_{k + m} \oplus x_{k + m}^{\prime}},{a_{1} \oplus a_{1}^{\prime}},\ldots \;,{{a_{l} \oplus a_{l}^{\prime}} = \underset{\underset{k + m}{}}{0,\ldots \mspace{11mu},0}},e_{1}^{a},\ldots \;,{e_{l}^{a}.}} & (32)\end{matrix}$

For an error in the bits x′₁, . . . x′_(k+m) with the error vectore^(x), the error syndrome S^(x) determined by the syndrome generatorSynd 110 and output at its output is equal to

$\begin{matrix}{\left( S^{x} \right)^{T} = {{H \cdot \left( e^{x} \right)^{T}} = {{\left( {H^{x},H^{a}} \right) \cdot \left( {e_{1}^{x},\ldots \mspace{11mu},e_{k + m}^{x},\underset{\underset{l}{}}{0,\ldots \mspace{11mu},0}} \right)^{T}} = {H^{x} \cdot \left( {e_{1}^{x},\ldots \;,e_{k + m}^{x}} \right)^{T}}}}} & (33)\end{matrix}$

and for an error in the bits a′₁, . . . , a′_(l) with the error vectore^(a), the error syndrome S^(y) determined by the syndrome generatorSynd 110 and output at its output is equal to

$\begin{matrix}{\left( S^{a} \right)^{T} = {{H \cdot \left( e^{a} \right)^{T}} = {{\left( {H^{x},H^{a}} \right) \cdot \left( {\underset{\underset{k + m}{}}{0,\ldots \mspace{11mu},0},e_{1}^{a},\ldots \mspace{11mu},e_{l}^{a}} \right)^{T}} = {H^{a} \cdot {\left( {e_{1}^{a},\ldots \mspace{11mu},e_{l}^{a}} \right)^{T}.}}}}} & (34)\end{matrix}$

The H matrix H=(H^(x), H^(a)) may be determined so that for any possibleerrors in the bits a′₁, . . . , a′_(l), i.e. for any combinations of e₁^(a), . . . , e_(l) ^(a) unequal

$\underset{\underset{l}{}}{0,\ldots \;,0},$

the error syndromes S^(a) determined by the syndrome generator accordingto equation (34) are different from all error syndromes S^(x) determinedaccording to equation (33) by the syndrome generator Synd 110, if 1-bitto t-bit errors occurred in the bits x′₁, . . . , x′_(k+m), whereinthese error syndromes are also pair-wise different for any possiblecombinations of the bits e₁ ^(x), . . . , e_(k+m) ^(x) with a single oneto t ones.

An error syndrome here is an m-component binary vector, wherein m is thenumber of check bits of the code C.

An error in the bits a′₁, . . . , a′_(l) may not be detected as anuncorrectable error by its error syndrome determined by the syndromegenerator Synd 110, if the syndrome

$\underset{\underset{m}{}}{0,\ldots \;,0},$

is associated to this particular bit combination a′₁, . . . , a′_(l) bythe syndrome generator. As there are in general 2^(m) differentm-component binary vectors and thus also 2^(m) different error syndromesof which 2^(m)−1 error syndromes are unequal

$\underset{\underset{m}{}}{0,\ldots \;,0},$

this is a very seldom case.

A corrector/detector Cor/Det 120 is connected downstream to the syndromegenerator Synd 110 in FIG. 28. The corrector/detector Cor/Det 120 ishere implemented so that when inputting an error syndrome S=Sx itoutputs a correction vector e^(cor)=e₁ ^(cor), . . . , e_(k+m) ^(cor),so that e₁ ^(cor)=e₁ ^(x), . . . , e_(k+m) ^(cor)=e_(k+m) ^(x) applieswhen a single one to t-bit error exists in the bits x′₁, . . . ,x′_(k+m) so that e₁ ^(x), . . . , e_(k+m) ^(x) comprises one to t ones.

It outputs a correction vector e₁ ^(cor)=0, . . . , e_(k+m) ^(cor)=0 sothat no correction takes place in the bits x′₁, . . . , x′_(k+m) whenS=0| or when S=S^(a)≠0| and e₁ ^(a), . . . , e_(l) ^(a) comprises atleast one 1. In the latter case, the error signal E takes on a valuewhich is different from the value of the error signal E when S=0 or whenS=S^(x) apply.

It is possible that the word width R of the error signal E is equalto 1. The word width R of the error signal E may also be greater than 1.It may then be differentiated using the error signal whether a 1-biterror occurred in the bits x′₁, . . . , x′_(k+m), a t-bit error occurredin the bits x′₁, . . . , x′_(k+m) or a random non-correctable erroroccurred in the bits a′₁, . . . , a′_(l).

In the following, an implementation example is to be considered, whereint=2, so that 1-bit errors and 2-bit errors in the bits x′₁, . . . ,x′_(k+m) may be corrected and (almost all) errors in the bits a′₁, . . ., a′_(l) shall be detected. 2·M=m applies.

A possible H matrix H=(H^(x), H^(a)) may be determined by

${H^{x} = {\left( {h_{1}^{x},\ldots \;,h_{k + m}^{x}} \right) = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \;,} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \;,} & \alpha^{3i_{k + m}}\end{pmatrix}}},{and}$$H^{a} = {\left( {h_{1}^{a},\ldots \;,h_{a}^{a}} \right) = {\begin{pmatrix}{0} & {\ldots \;,} & {0} \\\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}}\end{pmatrix}.}}$

Here, α is a generating element of the Galois field GF(2^(M)), α^(i) ¹ .. . , α^(i) ^(k+m) , α^(3i) ¹ . . . , α^(3i) ^(k+m) , α^(r) ¹ . . . ,α^(r) ^(l) are used in their vector presentation as M-component columnvectors, and the respective exponents of the generating element α are tobe interpreted modulo 2^(M)−1, as it is the standard in Galois fields.Here, k+m≦2^(M)−1.

0| denotes here an M-dimensional column vector with its M componentsequal to 0.

The exponents i₁, . . . , i_(k+m) of α^(i) ¹ . . . α^(i) ^(k+m) in thematrix H^(x) are selected so that they are pair-wise different.

The matrix H comprises m=2·M rows, so that the associated code Ccomprises m=2·M check bits.

It may be advantageous to select also the exponents r₁, . . . , r_(l) inthe matrix H^(a) so that they are pair-wise different, when l≦2^(M)−1applies. The m=2·M components of the columns h_(i) ^(x), i=1, . . . ,k+m of the matrix H^(x) consist of M first components belonging to α^(i)^(j) and M second components belonging α^(3·i) ^(j) . The m=2·Mcomponents of the columns h_(q) ^(a), q=1, . . . , l of the matrix H^(a)consists of M first components 0 which form an M-component 0 vector 0|and of M second components belonging to α^(r) ^(q) .

As axis a generating element of the Galois field GF(2^(M)), α^(r) ^(q)is unequal 0| for an arbitrary value of r_(q) and for any arbitraryM-component binary vector z≠0| there is a uniquely determined valuer_(z) with 1≦r_(z)<2^(M)−1, so that z=α^(r) ^(z) applies.

The matrix H^(x) is an H matrix of a shortened BCH code when k+m<2^(M)−1and the H matrix of an unshortened BCH code when k+m=2^(M)−1, whereinthe BCH code is a 1-bit error and 2-bit error correcting BCH code with acode distance d≧5, so that all error syndromes

S ^(x) =H ^(x)·(e ₁ ^(x) , . . . ,e _(k+m) ^(x))  (35)

for 1-bit errors and for 2-bit errors in the bits x′₁, . . . ,x′_(k+m)are pair-wise different and unequal 0|.

As the exponents i₁, . . . , i_(k+m) are pair-wise different, also α^(i)¹ , . . . , a^(i) ^(k+m) are pair-wise different and unequal 0|.

For a 1-bit error in the b-th bit 1≦b≦k+m the syndrome generator Synd110 then determines an error syndrome

${S^{x}(b)} = {\begin{matrix}\alpha^{i_{b}} \\\alpha^{3i_{b}}\end{matrix} \neq \begin{matrix}{0} \\{0}\end{matrix}}$

and for a 2-bit error in the a-th and b-th bit

${{S^{x}\left( {a,b} \right)} = {\begin{matrix}{\alpha^{i_{a}} + \alpha^{i_{b}}} \\{\alpha^{3i_{a}} + \alpha^{3i_{b}}}\end{matrix} \neq \begin{matrix}{0} \\z\end{matrix}}},$

wherein due to α^(i) ^(b) ≠α^(i) ^(a) also α^(i) ^(b) +α^(i) ^(a) ≠0|and + is the addition in GF(2^(M)) which corresponds to thecomponentwise XOR-ing of the M-component binary vectors in the usedvector presentation.

The sub-matrix

H ^(x1)=(α^(i) ¹ , . . . ,α^(i) ^(k+m) )

consisting of M rows is an H matrix of a linear code of the length k+mwith Q=M check bits. It here consists of the first Q=M rows of thematrix H^(x). The code associated with the H matrix H^(x1) is a Hammingcode with the code distance d=3, so that all 1-bit errors and all 2-biterrors in the bits x′₁, . . . , x′_(k+m) lead to an error syndromeS^(x1)≠0|, wherein S^(x1) consists of the first Q=M columns of the errorsyndrome S^(x) according to equation (35) with

S ^(x1) =H ^(x1)·(e ₁ ^(x) , . . . ,e _(k+m) ^(x))^(T)  (36)

The Q=M first rows of the matrix H^(a) which correspond to the Q rows ofthe matrix H^(x1) are the rows of the matrix H^(a) which each form anl-component row vector of only zeros. In the considered embodiment,these are the first Q=M rows of the matrix H^(y).

As a is a generating element of the Galois field GF(2^(M)), α_(p)≠0| forpε{0,1, . . . , M−2} applies, and each column of the matrix H^(a)comprises at least one 1.

FIG. 29 shows a possible implementation for the subcircuit Cor/Det 120of FIG. 28 for the considered implementation example.

In FIG. 29, m=2·M applies and the syndrome generator Synd designated byreference numeral 110 like in FIG. 28 outputs the subsyndrome S¹ on itsfirst M-bit wide output lines and outputs the subsyndrome S² on itssecond M-bit wide output lines.

The first M-bit wide output lines of the syndrome generator Synd 110which carry the subsyndrome S¹ are connected to M first inputs of acorrector Cor 2921 and simultaneously to M inputs of an NOR circuit 2922having M inputs and a 1-bit wide output. The second M-bit wide outputlines of the syndrome generator Synd 110 are connected to M secondinputs of the corrector Cor 2921 and simultaneously to M inputs of an ORcircuit 2923 having M inputs and a 1-bit wide output.

The 1-bit wide output of the NOR circuit 2922 is connected to a firstinput of an AND gate 2924 having two inputs and one output, wherein thesecond input of the AND gate 2924 is connected to the output of the ORcircuit 2923.

The AND gate 2924 outputs the error signal Eat its 1-bit wide output.Here E=1 applies when S¹=0| and S²≠0|, so that E=1 indicates an error inthe bits a′₁, . . . , a′_(l).

We have E=0 when S¹≠0| or S²=0| apply. Here, the subsyndrome S²=(S₁ ², .. . , S_(M) ²) being an M-digit binary number may in principle take on2^(M) different values.

If no error occurs in the bits a′₁, . . . , a′_(l), then S²=0|. It isalso possible that S²=0| when certain errors occurred in the bits a′₁, .. . , a′_(l), so that the following applies

H ^(a)·(e ₁ ^(a) , . . . ,e _(l) ^(a))^(T)=0|.

If all values α^(r) ¹ , α^(r) ² , . . . , α^(r) ^(l) are pair-wisedifferent it cannot happen that a 1-bit error or a 2-bit error in thebits a′₁, . . . , a′_(l) leads to S²=0|. If in addition to that allvalues α^(r) ¹ , α^(r) ² , . . . , α^(r) ^(l) comprise an odd number ofones, it cannot happen that a 1-bit error, a 2-bit error or a 3-biterror in the bits a′₁, . . . , a′_(l) leads to S²=0|.

If the values α^(r) ¹ , α^(r) ² , . . . , α^(r) ^(l) are determined sothat they comprise M linearly independent vectors and if it may beassumed that random errors in the bits a′₁, . . . , a′_(l) occur withthe same probability, then the probability that S²=0|, although a randomerror exists in the bits a′₁, . . . , a′_(l), is equal 2^(−M). Alreadyfor M=10 an error detection probability of greater than 99.9% resultsfor random errors in the bits α′₁, . . . , α′_(l).

The corrector Cor 2921 in FIG. 29 forms correction values e^(cor,x)=e₁^(cor,x), . . . , e_(k+m) ^(cor,x) for the bits x′₁, . . . , x′_(k+m) atits k+m-bit wide output.

For 1-bit and 2-bit errors in the bits x′₁, . . . , x′_(k+m) thecorrection values e^(cor,x)=e₁ ^(cor,x), . . . , e_(k+m) ^(cor,x) aredetermined by the corrector Cor 2921, for example using a 2-bit errorcorrecting BCH code and as it is described for example in Okano, H. andImai, K. “A construction method of high-speed decoders using ROM's forBose-Chaudhuri Hocqenhem and Reed Solomon codes”, IEEE trans. Comp. C36, pp. 1165-1171, 1987.

In an embodiment, t≧2 so that the linear t-bit error correcting code isan at least 2-bit error correcting code.

For the bits a′₁, . . . , a′_(l) no correction values are formed. Errorsin these bits are only detected.

FIG. 30 shows a further embodiment of the invention, wherein bits X′₁, .. . , X′_(k+m) are read out from an addressable memory Spei 12 at a readaddress a′=a′₁, . . . , a′_(l) and the bits x′₁, . . . , x′_(k+m), a′₁,. . . , a′_(l) may have resulted from errors from a codeword x₁, . . . ,x_(k+m), a₁, . . . , a_(l) of a linear code C, wherein the bits x₁, . .. , x_(k+m) were written into the memory at the write address a₁, . . ., a_(l). It is considered here that both the bits X₁, . . . , X_(k+m)written into the memory may be disturbed by errors into x′₁, . . . ,x′_(k+m)≠x₁, . . . , x_(k+m) when they are stored in the memory (forinstance by radiation) and further bits may be read out at an erroneousaddress a′=a′₁, . . . , a′_(l)≠a₁, . . . , a_(l)=a. The memory Spei 12comprises an address input at which either a write address a=a₁, . . . ,a_(l) or a read address a′=a′₁, . . . , a′_(l) may be applied. Controlsignals of the memory, like the write enable signal or the read enablesignal are not indicated in FIG. 30.

The bits x₁, . . . , x_(k+m) written into the memory Spei 12 at a writeaddress a=a₁, . . . , a_(l) for example consists of k data bits u₁, . .. , u_(k) and m check bits c₁, . . . , c_(m) which, together with thebits of the write address a₁, . . . , a_(l) at which the data bits andthe check bits were written into the memory, form a codeword c₁, . . . ,c_(m), u₁, . . . , u_(k), a₁, . . . , a_(l) of a linear code C of thelength n=k+m+l with m check bits. If the H matrix of the code C isdesignated by H, the following applies

${H \cdot \left\lbrack {\underset{\underset{{= x_{1}},\mspace{11mu} \ldots \mspace{14mu},x_{k + m}}{}}{c_{1},\ldots \mspace{14mu},c_{m},u_{1},\ldots \mspace{14mu},u_{k}},\underset{\underset{{= y_{1}},\mspace{11mu} \ldots \mspace{14mu},y_{l}}{}}{a_{1},\ldots \mspace{14mu},a_{l}}} \right\rbrack^{T}} = {\left( \underset{\underset{m}{}}{0,\ldots \mspace{14mu},0} \right)^{T}.}$

The bits x′₁, . . . , x′_(k+m) read out of the memory Spei 12 at theread address a′ are here applied to a first k+m-bit wide input of asyndrome generator Synd 110, at whose second l-bit wide input the bitsa′₁, . . . , a′_(l) of the read address are applied and which outputs anerror syndrome S at its m=2·M-bit wide output whose first M componentsform the subsyndrome S¹ and whose second M components form thesubsyndrome S². Here, the syndrome generator Synd 110 is configured sothat it provides the components of the error syndrome at its outputaccording to the H matrix H and M≧2.

The H matrix of the code C is here determined so that errors in bits ofthe bits X′₁, . . . , x′_(k+m) are corrected and errors in the addressbits y′₁=a′₁, . . . , y′_(l)=a′_(l) are detected.

If, for example, t=2 then 1-bit errors and 2-bit errors in the bits x′₁,. . . , x′_(k+m) are corrected.

The H matrix may here have the following form

$H^{x} = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \mspace{14mu},} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \mspace{14mu},} & \alpha^{3i_{k + m}}\end{pmatrix}$ and ${H^{a} = \begin{pmatrix}{0} & {\ldots \mspace{14mu},} & {0} \\\alpha^{r_{1}} & {\ldots \mspace{14mu},} & \alpha^{r_{l}}\end{pmatrix}},$

wherein α^(i) ¹ . . . , α^(i) ^(k+m) , α^(3i) ¹ . . . , α^(3i) ^(k+m) ,α^(r) ¹ . . . , α^(r) ^(l) are elements of the Galois field GF(2^(M))with a generating element a in their vector presentation as M-componentbinary vectors, 0| designates here an M-component zero vector, thevalues i₁, . . . , i_(k+m) are pair-wise different and 2·M=m and theexponents of the generating element a are to be interpreted modulo2^(M)−1.

The syndrome generator Synd 110 is configured so that it comprises, atits 2·M outputs, an error syndrome

S ^(T) =H·[x′ ₁ , . . . ,x′ _(k+m) ,a′ ₁ , . . . ,a′ _(l)]^(T) =H·[c′ ₁, . . . ,c′ _(m) ,u′ ₁ , . . . ,u′ _(k) ,a′ ₁ , . . . ,a′_(l)]^(T)  (37)

with m=2·M whose first M components form the subsyndrome S¹ and whosesecond M components form the subsyndrome S². The m=2·M bit output of thesyndrome generator Synd 110 is connected to the m-bit wide input of thesubcircuit Cor/Det′ 3037 which is configured so that at its firstk+m-bit wide output it forms a correction signal e^(cor,x)=e₁ ^(cor,x),. . . , e_(k+m) ^(cor,x) for the bits x′₁, . . . , x′_(k+m) which arecombined, according to their respective bit positions, into

x ^(cor) =x ₁ ^(cor) , . . . ,x _(k+m) ^(cor) =x′ ₁ ⊕e ₁ ^(cor,x) , . .. ,x′ _(k+m) ⊕e _(k+m) ^(cor,x)  (38)

in the XOR circuit 3038 which comprises k+m XOR gates, each having twoinputs and one output.

The subcircuit Cor/Det′ 3037 is here configured so that, at its second,here 2-bit wide output which carries the error signal E²,

-   -   it outputs 0, 0 when S¹=S²=0| applies and no error is indicated,    -   it outputs 0, 1 when S¹≠0| and (S¹)³=S² apply and it is        indicated that a 1-bit error exists in the bits x′₁, . . . ,        x′_(k+m),        and    -   it outputs 1, 0 when S¹≠0| applies and (S¹)³≠S² applies which        indicates that an error exists in the bits x′₁, . . . , x′_(k+m)        which is no 1-bit error.

Apart from that, the first M components of the output of the syndromegenerator Synd 110 are connected to the M-bit wide input of a NORcircuit 3034 having M inputs and one output, while the second Mcomponents of the output of the syndrome generator Synd 110 areconnected to the M-bit wide input of an OR circuit 3035 having M inputsand one output. The output of the NOR circuit 3034 and the OR circuit3035 are each connected to an input of an AND gate 3036 having twoinputs and one output wherein the same outputs a 1-bit error signal E¹at its output.

The subcircuit Cor/Det 120 of FIG. 28 is here formed by the describedsubcircuit Cor/Det′ 3037, the OR circuit 3035, the NOR circuit 3034 andthe AND gate 3036.

The error signal E¹ is equal to 1, when simulataneously S¹=0| and S²≠0|.E¹=1 may indicate an address error. The error signal E¹ is equal to 0,when S²=0| or when S¹≠0|. For E¹=0 no address error can exist, exceptfor very few specific constellations of the bits y′₁, . . . , y′_(l) (ora′₁, . . . , a′_(l)), the probability of which is 2^(−M), which aremapped to S²=0|.

FIG. 31 shows a further embodiment of the invention, wherein bits x′₁, .. . , x′_(k+m) are read out of an addressable memory Spei 12 at a readaddress a′=a′₁, . . . , a′_(l*), wherein y′₁, . . . , y′_(l)=A′₁, . . ., A′_(l)=f (a′₁, . . . , a′_(l*)) applies. Here, f:{0,1}^(l)*→{0,1}^(l)is a function which maps l*-digit address bits a₁, . . . , a_(l*) tol-digit compacted address bits A₁, . . . , A_(l), wherein l*>l applies.This mapping is done by a subcircuit 3142 having l* inputs and l outputsconnected to l second inputs of the syndrome generator Synd 3141. Thek+m first inputs of the syndrome generator Synd 3141 are connected tothe k+m data lines of the memory Spei 12 which carry the bits x′₁, . . ., x′_(k+m). The bits of the read address a′₁, . . . , a_(l*)′ areapplied to the l* inputs of the subcircuit 3142. The bits x′₁, . . . ,x′_(k+m), A′₁, . . . , A′_(l) may have resulted due to errors from acodeword x₁, . . . , x_(k+m), A₁, . . . , A_(l) of a linear code C,wherein the bits x₁, . . . , x_(k+m) were written into the memory at thewrite address a₁, . . . , a_(l*). It is considered here that both thebits x₁, . . . , x_(k+m) written into the memory, when they are readout, may be changed by errors into x′₁, . . . , x′_(k+m)≠x₁, . . . ,x_(k+m), and also bits may be read out at an erroneous address a′=a′₁, .. . , a_(l*)′≠a₁, . . . , a_(l*), so that also the compacted bits A′₁, .. . , A′_(l) formed from the read address a′₁, . . . , a′_(l*) may beerroneous. The memory Spei 12 comprises an address input to which eithera write address a=a₁, . . . , a_(l*) or a read address a′=a′₁, . . . ,a′_(l*) may be applied. Control signals of the memory, such as the writeenable signal or the read enable signal, are not illustrated in FIG. 31.

The bits x₁, . . . , x_(k+m) written into the memory Spei 12 at a writeaddress a=a₁, . . . , a_(l*) here, for example, consists of k data bitsu₁, . . . , u_(k) and m check bits c₁, . . . , c_(m) which form acodeword c₁, . . . , c_(m), u₁, . . . , u_(k), A₁, . . . , A_(l) of alinear code C of the length n=k+m+l having m check bits together withthe compacted bits A₁, . . . , A_(l) of the write address a₁, . . . ,a_(l*) at which the data bits and the check bits have been written intothe memory. If the H matrix of the code C is designated by H, thefollowing applies

${H \cdot \left\lbrack {c_{1},\ldots \mspace{14mu},c_{m},u_{1},\ldots \mspace{14mu},u_{k},A_{1},\ldots \mspace{14mu},A_{l}} \right\rbrack^{T}} = {\left( \underset{\underset{m}{}}{0,\ldots \mspace{14mu},0} \right)^{T}.}$

The bits x′₁, . . . , x′_(k+m) read out of the memory Spei 12 at theread address a′ are here applied to a first k+m-bit wide input of asyndrome generator Synd 3141 at whose second l-bit wide input the bitsA′₁, . . . , A′_(l) of the compacted bits of the read address areapplied and which outputs an error syndrome S at its m=2·M bit wideoutput whose first M components form the subsyndrome S¹ and whose secondM components form the subsyndrome S². The syndrome generator Synd 3141is configured so that it provides the components of the error syndromesaccording to the H matrix Hat its output and M≧2 applies. The H matrixof the code C is here determined so that errors in bits of the bits x′₁,. . . , x′_(k+m) are corrected and errors in compacted address bitsy′₁=A′₁, . . . , y′_(l)=A′_(l) are detected.

If, for example, t=2, then 1-bit errors and 2-bit errors in bits of thebits x′₁, . . . , x′_(k+m) are corrected and errors in the bits A′₁, . .. , A′_(l) which may, for example, be caused by errors in the bits a₁, .. . , a_(l*) are detected. The subcircuit 3142 may be configured so thatthe compacted address bits A₁, . . . , A_(l) are formed by l Booleanfunctions according to the following relation

y₁ = f₁(a₁, …  , a_(1*)) y₂ = f₂(a₁, …  , a_(1*))    ⋮y₁ = f₁(a₁, …  , a_(1*)),

l*>l applies and f₁, f₂, . . . , f_(l) each are l*-ary Booleanfunctions.

It may here be advantageous that

$y_{1},\ldots \mspace{14mu},{y_{l} \neq \underset{\underset{l}{}}{0,\ldots \mspace{14mu},0}}$

for all values of the addresses a₁, . . . , a_(l*) applies. It ispossible that

$\begin{matrix}\begin{matrix}\begin{matrix}{y_{1} = A_{1}} \\{y_{2} = A_{2}}\end{matrix} \\\vdots\end{matrix} \\{y_{l} = A_{l}}\end{matrix} = {K \cdot \begin{pmatrix}a_{1} \\a_{2} \\\vdots \\a_{l*}\end{pmatrix}}$

applies, wherein K is a binary (l, l*) matrix. In this case, thesubcircuit 3142 may be realized by XOR gates.

It is likewise possible that always y₁=A₁=1 applies and

$\begin{matrix}\begin{matrix}\begin{matrix}{y_{2} = A_{2}} \\{y_{3} = A_{3}}\end{matrix} \\\vdots\end{matrix} \\{y_{l} = A_{l}}\end{matrix} = {K^{+} \cdot \begin{pmatrix}a_{1} \\a_{2} \\\vdots \\a_{l*}\end{pmatrix}}$

applies, wherein K⁺ is a binary (l−1, l*) matrix. It then applies thaty₁, . . . , y_(l)=A₁, . . . , A_(l) is always unequal

$\underset{\underset{l}{}}{0,\ldots \mspace{14mu},0}.$

It is possible that due to an error all bits x′₁, . . . ,x′_(k+m) areerroneously equal to 0. Such an error may be called an All-0-error. Itis possible that the bits x′₁, . . . , x′_(k+m) are stored into memorycells which erroneously all take on the value 0. Then, the subsyndromeis S¹=0|. If the matrix H^(a) is determined so that

$\begin{matrix}{{H^{a} = \begin{pmatrix}{0} & {\ldots \mspace{14mu},} & {0} \\\alpha^{r_{1}} & {\ldots \mspace{14mu},} & \alpha^{r_{l}}\end{pmatrix}},} & (39)\end{matrix}$

applies, then the subsyndrome S² is equal

S ²=(α^(r) ¹ , . . . ,α^(r) ^(l*) )·(a ₁ , . . . ,a _(r) _(l*))^(T),  (40)

when the address bits are non-compacted and is equal to

S ²=(α^(r) ¹ , . . . ,α^(r) ^(l) )·(A ₁ , . . . ,A _(r) _(l))^(T),  (41)

when the address bits a₁, . . . , a_(l*) have been compacted into lcompacted address bits A₁, . . . , A_(l).

If, for example, m=2·M and l=M, then there are M different M-dimensionalcolumn vectors α^(r) ^(j) , j=1, . . . , M. They may be determined sothat the M-component column vectors α^(r) ¹ , . . . , α^(r) ^(M) arelinearly independent. If, apart from that, the M compacted address bitsA₁, . . . , A_(M) are determined so that they are unequal

$\underset{\underset{M}{}}{0,\ldots \mspace{14mu},0}$

for all occupations of the address bits a₁, . . . , a_(l*) then thesubsyndrome determined according to equation (41) is S²≠0| and the errorAll-0 is detected for a random value of the address.

For example, the following may be determined

$A_{1},A_{2},\ldots \mspace{14mu},{A_{M} = 1},A_{2},\ldots \mspace{14mu},{A_{M} \neq \underset{\underset{M}{}}{0,\ldots \mspace{14mu},0}}$

so that the first compacted address bit A₁ is always equal 1. In otherwords, an All-0 error in the bits x′₁, . . . , x′_(k+m) which may havebeen caused by the fact that all values of the memory cells into whichx₁, . . . , x_(k+m) was written erroneously take on the value 0 thenleads to an error syndrome with S¹=0| and S²≠0| and the error isdetected as a non-correctable error.

For example,

α^(r) ¹ , . . . ,α^(r) ^(M) =α⁰,α⁰, . . . ,α^(M) =I _(M)

may be determined, wherein I_(M) is the M-dimensional identity matrix.Then, the following applies

(S ²)^(T) =I _(M)·[1,A ₂ , . . . ,A _(M)]^(T)=[1,A ₂ , . . . ,A_(M)]^(T)≠0|^(T).

It is also possible that due to an error all bits x′₁, . . . , x′_(k+m)erroneously take on the value 1. Such an error may be called an All-1error.

If a matrix H^(x) is used for which

h ₁ ^(x) +h ₂ ^(x) + . . . +h _(k+m) ^(x)=0

applies, wherein 0 here designates the column vector with 2·M zeroes,then an All-1 error is detected analog to an All-0 error.

FIG. 32 shows a syndrome generator Synd 3251 having k+m first inputs forinputting the possibly erroneous bits x′₁, . . . , x′_(k+m) whichresulted from the correct bits x₁, . . . , x_(k+m) due to possibleerrors and having further l second inputs for inputting l possiblyerroneous identifier bits id′₁, . . . , id′_(l)=y′₁, . . . , y′_(l)which may have resulted due to possible errors from correct identifierbits id₁, . . . , id_(l). The identifier bits may for example representa password of a user. They may also serve for the identification of areceiver of the corrected data. For example, they may also be a binarilyencoded name of the receiver of data on a bus. If the input identifierbits do not correspond to the correct indicator bits, a non-correctableerror may be indicated which may, for example, lead to a reaction onsystem level, for example to an interrupt. Hence, the identifier bitsid₁, . . . , id_(l) are regarded and treated in approximately the samemanner as the address bits a₁, . . . , a_(l), or they may be also addedto the already used address bits.

In FIG. 32, the syndrome generator Synd 3251 comprises M first outputsfor outputting an M-component subsyndrome S¹ and M second outputs foroutputting a further M-component subsyndrome S².

In some applications, data bits or coded bits may also be protected by apassword against unauthorized access. The data bits can only bycorrectly decoded if the password or identifier bits are known to thereceiver. Identifier bits may be also denoted as identifier bits.

Unexpectedly, the concept of data protection by a password or byidentifier bits can be easily included into the concept of the inventionas will be now described by an example.

It will be, for instance, shown how an erroneous password or erroneousidentifier bits will result in an uncorrectable error. The correspondingerror signal of an uncorrectable error may for instance automaticallystop the readout of the data from the memory.

The error-free bits x₁, . . . , x_(k+m) may consist of m check bits c₁,. . . , c_(m) and k data bits u₁, . . . , u_(k), wherein the check bitsare formed so that

H·[c ₁ , . . . ,c _(m) ,u ₁ , . . . ,u _(k) ,id ₁ , . . . ,id_(l)]^(T)=0|

applies and c₁, . . . , c_(m), u₁, . . . , u_(k), id₁, . . . , id_(l) isa codeword of the considered code C.

FIG. 33 shows a further embodiment of the invention, wherein bits x′₁, .. . , x′_(k+m) are read out of an addressable memory Spei 12 at a readaddress a′=a′₁, . . . , a′_(l*) wherein y′₁, . . . , y′_(l)=A′₁, . . . ,A′_(l2), id′₁, . . . , id′_(l1) and A′₁, . . . , A′_(l2)=f(a′₁, . . . ,a′_(l*)) with l=l₁+l₂. Here, f:{0,1}^(l*)→{0,1}^(l2) is a function whichmaps l*-digit address bits a₁, . . . , a_(l*) to l2-digit compactedaddress bits A₁, . . . , A_(l2), wherein l*>l2. This mapping is done bya subcircuit 3362 having l* inputs and l2 outputs connected to l2 secondinputs of the syndrome generator Synd 3361, wherein the k+m data linesof the memory Spei 12 which carry the bits x′₁, . . . , x′_(k+m) areconnected to its k+m first inputs. Furthermore, l1 possibly erroneousidentifier bits id′₁, . . . , id′_(l1) which may have resulted frompossible errors of corrected identifier bits id₁, . . . , id_(l1) areapplied to further third l1-digit inputs of the syndrome generator Synd3361. The bits of the read address a′₁, . . . , a′_(l*) are applied tol* inputs of the subcircuit 3365. The bits x′₁, . . . , x′_(k+m), A′₁, .. . , A′_(l2), id′₁, . . . , id′_(l1) may have resulted due to errorsfrom a codeword x₁, . . . , x_(k+m), A₁, . . . , A_(l2), id₁, . . . ,id_(l1) of a linear code C, wherein the bits x₁, . . . , x_(k+n), havebeen written into the memory at the write address a₁, . . . , a_(l*).

It is considered here that both the bits x₁, . . . , x_(k+m) writteninto the memory, when they are read out, may be disturbed by errors inx′₁, . . . , x′_(k+m)≠x₁, . . . , x_(k+m) and that also bits may be readout at an erroneous address a′=a′₁, . . . , a′_(l*)≠a₁, . . . , a_(l*)so that also the compacted bits A′₁, . . . , A′_(l2), formed from theread address a′₁, . . . , a′_(l*) may be erroneous, and also that theidentifier bits id₁, . . . , id_(l1) may be different from the correctidentifier bits. The memory Spei 12 comprises an address input to whicheither a write address a=a₁, . . . , a_(l*) or a read address a′=a′₁, .. . , a′_(l*) may be applied. Control signals of the memory, like thewrite enable signal or the read enable signal, are not indicated in FIG.33. Also the indicator bits may be erroneous.

The bits x₁, . . . , x_(k+m) written into the memory Spei 12 at a writeaddress a=a₁, . . . , a_(l*) here for example consist of k data bits u₁,. . . , u_(k) and m check bits c₁, . . . , c_(m) which, together withthe compacted bits A₁, . . . , A_(l2) of the write address a₁, . . . ,a_(l*) at which the data bits and the check bits have been written intothe memory, and the identifier bits id₁, . . . , id_(l1), form acodeword c₁, . . . , c_(m), u₁, . . . , u_(k), A₁, . . . , A_(l2), id₁,. . . , id_(l1) of a linear code C of the length k+m+l with m checkbits. If the H matrix of the code C is designated by H, the followingapplies

${H \cdot \left\lbrack {c_{1},\ldots \mspace{14mu},c_{m},u_{1},\ldots \mspace{14mu},u_{k},A_{1},\ldots \mspace{14mu},A_{l\; 2},{id}_{1},\ldots \mspace{14mu},{id}_{l\; 1}} \right\rbrack^{T}} = {\left( \underset{\underset{m}{}}{0,\ldots \mspace{14mu},0} \right)^{T}.}$

The bits x′₁, . . . , x′_(k+m) read out of the memory Spei 12 at theread address a′ are here applied to a first k+m-bit wide input of asyndrome generator Synd 3361, at whose second l2-bit wide input the bitsA′₁, . . . , A′_(l2) of the compacted bits of the read address areapplied and at whose third l1-bit wide input the possibly erroneousidentifier bits id′₁, . . . , id′_(l1) are applied and which outputs atits m=2·M bit wide output an error syndrome S whose first M componentsform the subsyndrome S¹ and whose second M components form thesubsyndrome S². Here, the syndrome generator Synd 3361 is configured sothat it provides the components of the error syndromes according to theH matrix Hat its output and that M≧2 applies.

The H matrix of the code C is here determined so that errors in bits ofthe bits x′₁, . . . , x′_(k+m) are corrected and errors in the compactedaddress bits and in identifier bits, i.e. in the bits y′₁ . . . ,y′_(l)=A′₁, . . . , A′_(l2), id′₁, . . . , id′_(l1) are detected.

If, for example, t=2, then 1-bit errors and 2-bit errors in the bitsx′₁, . . . , x′_(k+m) are corrected and errors in the bits A′₁, . . . ,A′_(l2) which may for example have been caused by errors in the bits a₁,. . . , a_(l*), and errors in the bits id′₁, . . . , id′_(l1) aredetected.

FIG. 34 shows a syndrome generator Synd 3471 having n inputs to which ann-component word v′=v′₁, . . . , v′_(n) is applied which consists of acodeword v=v₁, . . . , v_(n) of a linear code C of the length n witht·M=m check bits.

The syndrome generator Synd 3471 comprises (t−1)·M first outputs foroutputting (t−1)·M first components of an error syndrome S determined bythe syndrome generator according to the H matrix of the code C whichform a subsyndrome S¹, and M further outputs for outputting M furthercomponents of the error syndrome which are designated by S². In thisembodiment, t≧3 is assumed. The Galois field used for determining the Hmatrix is GF(2^(M)).

The (t−1)·M first outputs of the syndrome generator Synd 3471 whichcarry the value S¹ are connected to the (t−1)·M inputs of an NOR circuit3473 having (t−1)·M inputs and one output which is connected to a firstinput of an AND gate 3475 having 2 inputs and one output. The M secondoutputs of the syndrome generator Synd 3471 which carry the value S² areconnected to the M inputs of an OR circuit 3474 having M inputs and oneoutput connected to the second input of the AND gate 3475 which outputsan error signal Eat its output. The error signal E is equal to 1, if the(t−1) components of S¹ are equal to 0 and if S² is not equal to 0|. Theerror signal E=1 indicates an address error.

The t·M outputs of the syndrome generator Synd 3471 are connected to t·Minputs of a corrector Cor 3472 which outputs a k+m-component correctionvalue e^(cor) for correcting possibly erroneous k+m bits of the word v′at its k+m outputs, wherein k+m designates the number of bits (length ofthe portion of the word of v′) for which an error correction is inprinciple possible, up to t bit errors within said set of k+m bits.

If t=3, the H matrix of the code C may have the following form

H=(H ^(x) ,H ^(a))

with

$H^{x} = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \mspace{14mu},} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \mspace{14mu},} & \alpha^{3i_{k + m}} \\\alpha^{5i_{1}} & {\ldots \mspace{14mu},} & \alpha^{5i_{k + m}}\end{pmatrix}$ and ${H^{a} = \begin{pmatrix}{0} & {\ldots \mspace{14mu},} & {0} \\{0} & {\ldots \mspace{14mu},} & {0} \\\alpha^{r_{1}} & {\ldots \mspace{14mu},} & \alpha^{r_{1}}\end{pmatrix}},$

wherein α^(i) ¹ . . . , α^(i) ^(k+m) , α^(3i) ¹ . . . , α^(3i) ^(k+m) ,α^(5i) ¹ . . . , α^(5i) ^(k+m) , α^(r) ¹ . . . , α^(r) ^(l) elements ofthe Galois field GF(2^(M)) in their vector presentation are M-componentbinary vectors, 0| designates an M-component zero vector, the values i₁,. . . , i_(k+m) are a pair-wise different, and we have 3·M=m and theexponents of the generating element a are to be interpreted modulo2^(M)−1.

If t=4, the H matrix of the code C may have the following form

H=(H ^(x) ,H ^(a))

with

$H^{x} = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \mspace{11mu},} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \mspace{14mu},} & \alpha^{3i_{k + m}} \\\alpha^{5i_{1}} & {\ldots \mspace{14mu},} & {\alpha^{5i}}_{k + m} \\\alpha^{7i_{1}} & {\ldots \mspace{14mu},} & \alpha^{7i_{k + m}}\end{pmatrix}$ and ${H^{a} = \begin{pmatrix}{0} & {\ldots \mspace{11mu},} & {0} \\{0} & {\ldots \mspace{11mu},} & {0} \\{0} & {\ldots \mspace{14mu},} & {0} \\\alpha^{r_{1}} & {\ldots \mspace{14mu},} & \alpha^{r_{1}}\end{pmatrix}},$

wherein α^(i) ¹ . . . , α^(i) ^(k+m) , α^(3i) ¹ . . . , α^(3i) ^(k+m) ,α^(5i) ^(1 . . . , α) ^(5i) ^(k+m) , α^(7i) ¹ . . . , α^(7i) ^(k+m) ,α^(r) ¹ . . . , α^(r) ^(l) are elements of the Galois field GF(2^(M))with a generating element a in their vector representation asM-component binary vectors, 0| designates an M-component zero vector,the values i₁, . . . , i_(k+m) are all pair-wise different, and 4·M=mapplies and the exponents of the generating element a are to beinterpreted modulo 2^(M)−1.

FIG. 35 shows an embodiment of the invention where the parity of bits tobe corrected is integrated into the formation of the H matrix of theused code C.

There is a syndrome generator Synd 3581 having n inputs to which ann-component word v′=v′₁, . . . , v′_(n)=x′₁, . . . , x′_(k+m), y′₁, . .. , y′_(l) is applied which may have resulted due to errors from acodeword v=v₁, . . . , v_(n) of a linear code C of the length n having2·M+1=m check bits.

The syndrome generator Synd 3581 comprises a first 1-bit wide output foroutputting a first component S^(P) of an error syndrome S determined bythe syndrome generator according to the H matrix of the code C, M secondoutputs for outputting M second components of an error syndrome Sdetermined by the syndrome generator according to the H matrix of thecode C designated by S¹ and M further outputs for outputting M furthercomponents of the error syndrome designated by S². In this embodiment,t=2 is assumed. The syndrome S^(P) is the component of the errorsyndrome S associated with the parity. The Galois field used fordetermining the H matrix is GF(2^(M)).

The M second outputs of the syndrome generator carrying the value S¹ areconnected to the M inputs of an NOR circuit 3584 having M inputs and oneoutput connected to a first input of an AND gate 3586 having two inputsand one output. The M third outputs of the syndrome generator carryingthe value S² are connected to the M inputs of an OR circuit 3585 havingM inputs and one output connected to the second input of the AND gate3586 which outputs an error signal E¹ at its output.

Apart from that, the 2·M+1 outputs of the syndrome generator Synd 3581are connected to 2·M+1 inputs of a corrector/detector Cor/Det 3587 whichoutputs at its k+m first outputs a k+m-component correction valuee^(cor) for correcting possible erroneous k+m bits x′₁, . . . , x′_(k+m)of the word v′ and which outputs at further R outputs a further errorsignal E², wherein in the considered embodiment R=2.

One possible H matrix is

H=(H ^(x) ,H ^(a))

with

$H^{x} = \begin{pmatrix}1 & \ldots & 1 \\\alpha^{i_{1}} & \ldots & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & \ldots & \alpha^{3i_{k + m}}\end{pmatrix}$ and $H^{a} = \begin{pmatrix}0 & {\ldots \mspace{11mu},} & 0 \\\alpha^{r_{1}} & {\ldots \mspace{14mu}} & \alpha^{r_{1}} \\{0} & {\ldots \mspace{14mu}} & {0}\end{pmatrix}$ and $H^{x^{\prime}} = \begin{pmatrix}\alpha^{i_{1}} & \ldots & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & \ldots & \alpha^{3i_{k + m}}\end{pmatrix}$ and $H^{a^{\prime}} = \begin{pmatrix}\alpha^{r_{1}} & \ldots & \alpha^{r_{1}} \\{0} & \ldots & {0}\end{pmatrix}$

The matrices H^(x′) and H^(a′) here each consist of the lines 2 to 2M+1of the matrices H^(x) and H^(a).

The first component S^(P) of the error syndrome is determined by

S ^(P) =x′ ₁ ⊕x′ ₂ ⊕ . . . ⊕x′ _(k+m).  (42)

The following applies If a 1-bit error exists in the bits x′₁, . . . ,x′_(k+m), S^(P)=1, (S¹)³=S² applies and the corrector/detector Cor/Det3587 is configured so that E² takes on a first value, for example 0, 1.

-   -   If a 2-bit error exists in the bits x′₁, . . . , x′_(k+m),        S^(P)=1, (S¹)³=S² applies and the corrector/detector Cor/Det        3587 is configured so that E² takes on a second value, for        example 1, 0.    -   If a 3-bit error exists in the bits x′₁, . . . , x′_(k+m),        S^(P)=0, (S¹)³≠S² applies and the corrector/detector Cor/Det        3587 is configured so that E² takes on a third value, for        example 1, 1.

It is further possible to include the parity so that a H matrixH=(H^(x), H^(a)) is formed with

$H^{x} = \begin{pmatrix}\alpha^{i_{1}} & \ldots & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & \ldots & \alpha^{3i_{k + m}}\end{pmatrix}$ and $H^{y} = \begin{pmatrix}\alpha^{r_{1}} & \ldots & \alpha^{r_{l}} \\{0} & \ldots & {0}\end{pmatrix}$

so that only such exponents i₁, . . . , i_(k+m) of the generatingelement a are used that α^(i) ¹ , . . . , α^(i) ^(k+m) in their vectorrepresentation in GF(2^(M)) as M-component column vectors each comprisean odd number of ones. Then, the parity of the bits x′₁, . . . ,x′_(k+m) is determined by the XOR combination of the components of S¹.

The different representations of elements of a Galois field are known tothe person skilled in the art.

For a better understanding of the invention, with reference to anembodiment, the determination of a H matrix with elements of a Galoisfield GF(2^(M)) is now described, as it is for example described in Lin,S. and Costello, D. “Error Control Coding”, Prentice Hall, 1983 on pages148 and 149 with reference to page 33.

In this respect, the H matrix

$\begin{matrix}{H = \begin{pmatrix}\alpha^{0} & \alpha^{1} & \alpha^{2} & {\ldots\alpha}^{14} \\\alpha^{0} & \alpha^{3} & \alpha^{6} & {\ldots\alpha}^{12}\end{pmatrix}} & (43)\end{matrix}$

with elements of the Galois field GF(2^(M)) with the modular polynomialp(X)=1+X+X⁴ is to be considered. The exponents of the generating elementa are to be interpreted modulo 2⁴1=15, so that e.g. (3·14=42=12 modulo15) applies.

The 16 elements of the Galois field may be given in the exponentialrepresentation, in the polynomial representation and in the vector ortuple representation, wherein the different representations areillustrated in table 1.

TABLE 1 exponential polynomial representation representation columnvector 0 0 0 0 0 0 α⁰ 1 1 0 0 0 α¹ x¹ 0 1 0 0 α² x² 0 0 1 0 α³ x³ 0 0 01 α⁴ 1 + x 1 1 0 0 α⁵ x + x² 0 1 1 0 α⁶ x² + x³ 0 0 1 1 α⁷ 1 + x + x³ 11 0 1 α⁸ 1 + x² 1 0 1 0 α⁹ x + x³ 0 1 0 1 α¹⁰ 1 + x + x² 1 1 1 0 α¹¹ x +x² + x³ 0 1 1 1 α¹² 1 + x + x² + x³ 1 1 1 1 α¹³ 1 + x² + x³ 1 0 1 1 α¹⁴1 + x³ 1 0 0 1

As according to table 1 the following applies: α⁰=[1000]^(T),α¹=[0100]^(T), α²=[0010]^(T), α³=[0001]^(T), α⁶=[0011]^(T), . . . ,α¹²=[1111]^(T), α¹⁴=[1001], for the matrix (43) the following results

$H = {\begin{pmatrix}1 & 0 & 0 & \ldots & 1 \\0 & 1 & 0 & \ldots & 0 \\0 & 0 & 1 & \ldots & 0 \\0 & 0 & 0 & \ldots & 1 \\1 & 0 & 0 & \ldots & 1 \\0 & 0 & 0 & \ldots & 1 \\0 & 0 & 1 & \ldots & 1 \\0 & 1 & 1 & \ldots & 1\end{pmatrix}.}$

Some embodiments have been described with respect to columns of theabove-described matrices. However, the person skilled in the artunderstands that all concepts described above are equally applicable torows of the above-described matrices by employing the above-describedconcepts.

Although some aspects have been described in the context of anapparatus, it is clear that these aspects also represent a descriptionof the corresponding method, where a block or device corresponds to amethod step or a feature of a method step. Analogously, aspectsdescribed in the context of a method step also represent a descriptionof a corresponding unit or item or feature of a corresponding apparatus.

Depending on certain implementation requirements, embodiments ofembodiments can be implemented in hardware or in software. Theimplementation can be performed using a digital storage medium, forexample a floppy disk, a DVD, a CD, a ROM, a PROM, an EPROM, an EEPROMor a FLASH memory, having electronically readable control signals storedthereon, which cooperate (or are capable of cooperating) with aprogrammable computer system such that the respective method isperformed.

Some embodiments according to embodiments comprise a non-transitory datacarrier having electronically readable control signals, which arecapable of cooperating with a programmable computer system, such thatone of the methods described herein is performed.

Generally, embodiments of the present invention can be implemented as acomputer program product with a program code, the program code beingoperative for performing one of the methods when the computer programproduct runs on a computer. The program code may for example be storedon a machine readable carrier.

Other embodiments comprise the computer program for performing one ofthe methods described herein, stored on a machine readable carrier.

In other words, an embodiment of the inventive method is, therefore, acomputer program having a program code for performing one of the methodsdescribed herein, when the computer program runs on a computer.

A further embodiment of the inventive methods is, therefore, a datacarrier (or a digital storage medium, or a computer-readable medium)comprising, recorded thereon, the computer program for performing one ofthe methods described herein.

A further embodiment of the inventive method is, therefore, a datastream or a sequence of signals representing the computer program forperforming one of the methods described herein. The data stream or thesequence of signals may for example be configured to be transferred viaa data communication connection, for example via the Internet.

A further embodiment comprises a processing means, for example acomputer, or a programmable logic device, configured to or adapted toperform one of the methods described herein.

A further embodiment comprises a computer having installed thereon thecomputer program for performing one of the methods described herein.

In some embodiments, a programmable logic device (for example a fieldprogrammable gate array) may be used to perform some or all of thefunctionalities of the methods described herein. In some embodiments, afield programmable gate array may cooperate with a microprocessor inorder to perform one of the methods described herein. Generally, themethods are performed by any hardware apparatus.

While this invention has been described in terms of several advantageousembodiments, there are alterations, permutations, and equivalents whichfall within the scope of this invention. It should also be noted thatthere are many alternative ways of implementing the methods andcompositions of the present invention. It is therefore intended that thefollowing appended claims be interpreted as including all suchalterations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

The above described embodiments are merely illustrative for theprinciples of the present invention. It is understood that modificationsand variations of the arrangements and the details described herein willbe apparent to others skilled in the art. It is the intent, therefore,to be limited only by the scope of the impending patent claims and notby the specific details presented by way of description and explanationof the embodiments herein.

Although each claim only refers back to one single claim, the disclosurealso covers any conceivable combination of claims.

1. A syndrome generator for forming an error syndrome of a linear code Cof length n with an H-matrix H=(h₁, . . . , h_(n)) of n columns h₁, . .. , h_(n) of m components each such that the H-matrix is an (m,n)-matrix, wherein a codeword v=v₁, . . . , v_(n) of the code Ccomprises a first subword x₁, . . . , x_(k+m) of length k+m and a secondsubword a₁, . . . , a_(l) of length l with n=k+m+l, wherein the code Cis configured for correcting 1, . . . , t-bit errors in bits of thefirst subword and to detect 1, . . . , l bit errors in bits of thesecond subword so that the columns of the H-matrix H corresponding tothe bits of the first subword are forming a first (m, k+m)-sub-matrixH^(x)=(h₁ ^(x), . . . , h_(k+m) ^(x)) and so that the columns of theH-matrix H corresponding to the bits of the second subword are forming asecond sub-matrix H^(a)=(h₁ ^(a), . . . , h_(l) ^(a)), wherein alllinear combinations of up to t columns of the first submatrix H^(x),which do not result in the zero vector, are pairwise different, andwherein all linear combinations of the columns of the second submatrixH^(a) are different from all linear combinations of up to t columns ofthe first sub-matrix H_(x), which do not result in the zero vector,wherein t≧1, k>0, k+m≧4, and l>t+1.
 2. The syndrome generator accordingto claim 1, wherein at least a portion of the first subword x₁, . . . ,x_(k+m)=u₁, . . . , u_(k), c₁, . . . , c_(m) is stored in a memory underan address.
 3. The syndrome generator according to claim 1, wherein atleast one of the bits a₁, . . . , a_(l) of the second subword is notstored in a memory, wherein one or more bits of the first subword arestored.
 4. The syndrome generator according to claim 1, wherein thesecond subword a₁, . . . , a_(l) are address bits or bits derived fromaddress bits of an address under which at least a portion of the firstsubword x₁, . . . , x_(k+m)=u₁, . . . , u_(k), c₁, . . . , c_(m) isstored.
 5. The syndrome generator according to claim 1, wherein at leasta subset of the bits a₁, . . . , a_(l) of the second subword areidentifier bits.
 6. The syndrome generator according to claim 1, whereinthe second sub-matrix H^(y) comprises two rows, the components of whichare constant in said two rows.
 7. The syndrome generator according toclaim 1, wherein Q rows of the sub-matrix H^(x) with Q<m form a paritycheck matrix H^(x1) of an at least (t)-bit error detecting code of thelength k+m with Q check bits and the sub-matrix H^(x) is a parity checkmatrix of a t-bit error correcting code of the length k+m with m checkbits, wherein the l components of the Q rows of the sub-matrix H^(y)which correspond to the Q rows forming the parity check matrix H^(x1) ofthe error detecting code consist of l zeroes, and wherein all columns ofthe sub-matrix H^(y) comprise at least one component equal to
 1. 8. Thesyndrome generator according to claim 7, wherein all columns of thesub-matrix H^(y) are pair-wise different.
 9. The syndrome generatoraccording to claim 1, wherein t=2, the parity check matrix H=(H^(x),H^(y)) is a (m, n) matrix and 2·M rows of the parity check matrix H forma matrix (H^(x′), H^(y′)) with $H^{x^{\prime}} = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \;,} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \;,} & \alpha^{3i_{k + m}}\end{pmatrix}$ and wherein H^(y′) is defined as${H^{y^{\prime}} = {{\begin{pmatrix}\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}} \\{0} & {\ldots \;,} & {0}\end{pmatrix}\mspace{14mu} {or}\mspace{14mu} H^{y^{\prime}}} = \begin{pmatrix}{0} & {\ldots \;,} & {0} \\\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}}\end{pmatrix}}},$ wherein α^(i) ¹ . . . , α^(i) ^(k+m) , α^(3i) ¹ . . ., α^(3i) ^(k+m) , α^(r) ¹ . . . , α^(r) ^(l) are elements of a Galoisfield GF(2^(M)) with a generating element a in their vector presentationas M-component binary vectors, 0| designates an M-component zero vector,the values i₁, . . . , i_(k+m) are pair-wise different and 2·M≦m and theexponents of the generating element a are to be regarded as modulo2^(M)−1.
 10. The syndrome generator according to claim 1, wherein t=3,the parity check matrix H=(H^(x), H^(y)) is an (m, n) matrix and 3·Mrows of the parity check matrix H form a matrix (H^(x′), H^(y′)) with$H^{x^{\prime}} = \begin{pmatrix}\alpha^{i_{1}} & {\ldots \;,} & \alpha^{i_{k + m}} \\\alpha^{3i_{1}} & {\ldots \;,} & \alpha^{3i_{k + m}} \\\alpha^{5i_{1}} & {\ldots \;,} & \alpha^{5i_{k + m}}\end{pmatrix}$ and wherein H^(y′) is defined as${H^{y^{\prime}} = \begin{pmatrix}{0} & {\ldots \;,} & {0} \\{0} & {\ldots \;,} & {0} \\\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}}\end{pmatrix}},{{{or}\mspace{14mu} H^{y^{\prime}}} = \begin{pmatrix}{0} & {\ldots \;,} & {0} \\\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}} \\{0} & {\ldots \;,} & {0}\end{pmatrix}},{{{or}\mspace{14mu} H^{y^{\prime}}} = \begin{pmatrix}\alpha^{r_{1}} & {\ldots \;,} & \alpha^{r_{l}} \\{0} & {\ldots \;,} & {0} \\{0} & {\ldots \;,} & {0}\end{pmatrix}},$ wherein α^(i) ¹ . . . , α^(i) ^(k+m) , α^(3i) ¹ . . . ,α^(3i) ^(k+m) , α^(5i) ¹ . . . α^(5i) ^(k+m) , α^(r) ¹ . . . , α^(r)^(l) are elements of a Galois field GF(2^(M)) in their vectorpresentation as m-component binary vectors, 0| designates an M-componentzero vector, the values i₁, . . . , i_(k) are all pair-wise differentand 3·M+2≦m and the exponents of the generating element a are to beinterpreted modulo 2^(M)−1.
 11. The syndrome generator according toclaim 1, wherein t≧2, the sub-matrix H^(x) is the parity check matrix ofa shortened t-bit correcting BCH code in a Galois field GF(2^(M)) in aseparated form of the length k and the sub-matrix H^(y) comprises lcolumns and at least m=[(t−1)·M] rows, wherein all l components of(t−1)·M of the rows of H^(y) are equal to
 0. 12. The syndrome generatoraccording to claim 11, wherein the components of the first (t−1)·M rowsof the sub-matrix H^(y) are equal to
 0. 13. The syndrome generatoraccording to claim 1, wherein the bits y₁, . . . , y_(l) are compactedaddress bits formed from l* address bits a₁, . . . , a_(l*) according tothe following relation $\begin{matrix}{y_{1} = {f_{1}\left( {a_{1},\ldots \mspace{11mu},a_{l*}} \right)}} \\{y_{2} = {f_{2}\left( {a_{1},\ldots \mspace{11mu},a_{l*}} \right)}} \\\vdots \\{{y_{l} = {f_{l}\left( {a_{1},\ldots \mspace{11mu},a_{l*}} \right)}},}\end{matrix}$ l*>k applies and f₁, f₂, . . . , f_(l) are each l*-aryBoolean functions.
 14. The syndrome generator according to claim 13,characterized in that $\begin{matrix}y_{1} \\y_{2} \\\vdots \\y_{l}\end{matrix} = {K \cdot \begin{pmatrix}a_{1} \\a_{2} \\\vdots \\a_{l*}\end{pmatrix}}$ applies, wherein K is a binary (l, l*) matrix.
 15. Thesyndrome generator according to claim 13, characterized in that y₁=1 and$\begin{matrix}y_{2} \\y_{3} \\\vdots \\y_{l}\end{matrix} = {K^{+} \cdot \begin{pmatrix}a_{1} \\a_{2} \\\vdots \\a_{l*}\end{pmatrix}}$ applies, wherein K⁺ is a binary (l−1, l*) matrix. 16.The syndrome generator according to claim 13, characterized in that$y_{1},\ldots \mspace{11mu},{y_{l} \neq \underset{\underset{l}{}}{0,\ldots \mspace{11mu},0}}$for all values of the addresses a₁, . . . , a_(l*).
 17. The syndromegenerator according to claim 16, wherein l*=l and the l columns of thesubmatrix H^(y) are linearly independent.
 18. The syndrome generatoraccording to claim 1, wherein a component-wise XOR sum of the columns ofthe submatrix H^(x) is equal to$\left( \underset{\underset{m}{}}{0,\ldots \mspace{11mu},0} \right)^{T}.$19. The syndrome generator according to claim 1, wherein a non-emptysubset {y_(i) ₁ , . . . , y_(i) _(q) } of the bits y₁ . . . , y_(l) areidentifier bits id_(i) ₁ , . . . , id_(i) _(q) with 1≦q≦l.
 20. Thesyndrome generator according to claim 19, wherein 1≦q<l, a non-emptyproper subset {y_(i) ₁ , . . . , y_(i) _(q) } of the bits y₁ . . . ,y_(l) are identifier bits id_(i) ₁ , . . . , id_(i) _(q) , and a furthernon-empty proper subset {y_(i) ₁ , . . . , y_(j) _(p) } of the bits y₁ .. . , y_(l) which are no identifier bits are address bits or bitsderived from address bits, and wherein q+p≦l applies.
 21. The syndromegenerator according to claim 1, wherein the H-matrix H=(h₁, . . . ,h_(n)) comprises a plurality of rows, wherein one of the plurality ofrows is different from another one of the plurality of rows, such thatfor i=1, . . . , m+k, for the column h_(i) ^(x) of the submatrixH^(x)=(h₁ ^(x), . . . , h_(k+m) ^(x)) the pair of components whichbelong to the column hi and also either to said one of the plurality ofrows or to said another one of the plurality of rows are different from[1, 1] and such that for j=1, . . . , l for the column h_(j) ^(a) of thesubmatrix H^(a)=(h₁ ^(a), . . . , h_(l) ^(a)) the pair of componentswhich belong to the column h_(j) ^(a) and also belong either to said oneof the plurality of rows or to said another one of the plurality of rowsare equal to [1, 1] and wherein all columns of the H-matrix H comprisean odd number of 1s.
 22. The syndrome generator according to claim 21,wherein the matrix H_(a) is defined according to$H^{a} = {\left( {h_{1}^{a},\ldots \mspace{11mu},h_{l}^{a}} \right) = \begin{pmatrix}\underset{\underset{m^{\prime}}{}}{1,\ldots \mspace{11mu},1} \\\underset{\underset{m^{\prime}}{}}{1,\ldots \mspace{11mu},1} \\L_{m^{\prime}}\end{pmatrix}}$ wherein l=m′=m−2, wherein L_(m′) is an (m′, m′)-matrix,wherein all columns of the H-matrix H comprise an odd number of 1s, andwherein the m′ columns of the matrix L_(m′) are lineary independent. 23.The syndrome generator according to claim 22, wherein the matrix L_(m′)is an m′-dimensional identity matrix.
 24. A circuitry comprising asyndrome generator configured to generate a syndrome based on a paritycheck matrix and a binary word comprising a first set of bits and asecond set of bits, wherein for the first set of bits an errorcorrection of one or more correctable bit errors within the first set isprovided by the parity check matrix and for the second set of bits anerror detection of one or more detectable bit errors within the secondset is provided by the parity check matrix; wherein the parity checkmatrix comprises a first subset of columns that are associated with thefirst set of bits within the binary word, and a second subset of columnsthat are associated with the second set of bits within the binary word;and wherein syndromes generated by the first subset of columns in caseone of the one or more correctable errors occurs within the first set ofbits are all pairwise different for the one or more correctable errorsand are also different from all syndromes generated by the second subsetof columns in case an arbitrary error occurs within the second set ofbits; or wherein the parity check matrix comprises a first subset ofrows that are associated with the first set of bits within the binaryword, and a second subset of rows that are associated with the secondset of bits within the binary word; and wherein syndromes generated bythe first subset of rows in case one of the one or more correctableerrors occurs within the first set of bits are all pairwise differentfor the one or more correctable errors and are also different from allsyndromes generated by the second subset of columns in case an arbitraryerror occurs within the second set of bits.
 25. A circuitry according toclaim 24, wherein the first subset of columns forms an error correctingparity check matrix for the correctable bit errors that is based on agenerating element of a Galois field, and wherein the second subset ofcolumns forms an error detecting parity check matrix for the detectableerrors that is based on the same generating element of the same Galoisfield, or wherein the first subset of rows forms the error correctingparity check matrix for the correctable bit errors that is based on agenerating element of the Galois field, and wherein the second subset ofrows forms the error detecting parity check matrix for the detectableerrors that is based on the same generating element of the same Galoisfield.